Ramesh Harjani

4.8k total citations
225 papers, 3.4k citations indexed

About

Ramesh Harjani is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Hardware and Architecture. According to data from OpenAlex, Ramesh Harjani has authored 225 papers receiving a total of 3.4k indexed citations (citations by other indexed papers that have themselves been cited), including 213 papers in Electrical and Electronic Engineering, 81 papers in Biomedical Engineering and 30 papers in Hardware and Architecture. Recurrent topics in Ramesh Harjani's work include Radio Frequency Integrated Circuit Design (98 papers), Analog and Mixed-Signal Circuit Design (76 papers) and Advancements in PLL and VCO Technologies (72 papers). Ramesh Harjani is often cited by papers focused on Radio Frequency Integrated Circuit Design (98 papers), Analog and Mixed-Signal Circuit Design (76 papers) and Advancements in PLL and VCO Technologies (72 papers). Ramesh Harjani collaborates with scholars based in United States, South Korea and Canada. Ramesh Harjani's co-authors include L.R. Carley, Rob A. Rutenbar, Liang Dai, Sudhir S. Kudva, Bodhisatwa Sadhu, Byunghoo Jung, Sachin S. Sapatnekar, Mustafijur Rahman, Satwik Patnaik and Meghna Madhusudan and has published in prestigious journals such as Nano Letters, IEEE Access and IEEE Communications Magazine.

In The Last Decade

Ramesh Harjani

213 papers receiving 3.3k citations

Peers

Countries citing papers authored by Ramesh Harjani

Since Specialization

Citations

This map shows the geographic impact of Ramesh Harjani's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Ramesh Harjani with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Ramesh Harjani more than expected).

Fields of papers citing papers by Ramesh Harjani

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Ramesh Harjani. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Ramesh Harjani. The network helps show where Ramesh Harjani may publish in the future.

Co-authorship network of co-authors of Ramesh Harjani

This figure shows the co-authorship network connecting the top 25 collaborators of Ramesh Harjani. A scholar is included among the top collaborators of Ramesh Harjani based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Ramesh Harjani. Ramesh Harjani is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Minimum Unit Capacitance Calculation for Capacitor Arrays in Binary-Weighted and Split DACs 2024 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·(unknown), Ramesh Harjani, Sachin S. Sapatnekar	0
2	MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs 2024 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·(unknown), (unknown), Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu	1
3	Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients 2024 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Arvind Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, (unknown), Ramesh Harjani, Sachin S. Sapatnekar	1
4	A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process 2024 ·IEEE Access ·(unknown), Joonho Gil, (unknown), Kyu‐Jin Cho, (unknown), Eun‐Seong Kim, (unknown), Ramesh Harjani, Nam‐Young Kim, (unknown)	2
5	Analyzing the Impact of FinFET Self-Heating on the Performance of RF Power Amplifiers 2024 ·(unknown), Sai-Wang Tam, (unknown), Vidya A. Chhabria, Ramesh Harjani, Sachin S. Sapatnekar	1
6	A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts 2023 ·ACM Transactions on Design Automation of Electronic Systems ·(unknown), Meghna Madhusudan, Arvind Sharma, (unknown), Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar	5
7	GNN-Based Hierarchical Annotation for Analog Circuits 2023 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Kishor Kunal, (unknown), Meghna Madhusudan, (unknown), Arvind Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar	12
8	Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs 2023 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·(unknown), Arvind Sharma, (unknown), Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar	8
9	Pseudo-Reference Counter-Based FLL for 6 Gb/s Reference-Less CDR in 65-nm CMOS 2022 ·IEEE Transactions on Circuits & Systems II Express Briefs ·(unknown), Ramesh Harjani, (unknown)	2
10	Performance-driven Wire Sizing for Analog Integrated Circuits 2022 ·ACM Transactions on Design Automation of Electronic Systems ·(unknown), (unknown), Meghna Madhusudan, (unknown), Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu	3
11	Linear Characteristic Analysis of High-Resolution Counter-Based Frequency Detector in Type-I Digital PLL 2021 ·IEEE Transactions on Circuits & Systems II Express Briefs ·(unknown), Joonho Gil, Ramesh Harjani	1
12	Aging of Current DACs and its Impact in Equalizer Circuits 2021 ·(unknown), (unknown), Ramesh Harjani, Sachin S. Sapatnekar	3
13	GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits 2020 ·Kishor Kunal, (unknown), Meghna Madhusudan, (unknown), Arvind Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar	55
14	Observation of High Spin-to-Charge Conversion by Sputtered Bismuth Selenide Thin Films at Room Temperature 2019 ·Nano Letters ·Mahendra DC, Junyang Chen, T. Peterson, (unknown), Bin Ma, (unknown), Ramesh Harjani, Jian‐Ping Wang	38
15	Jitter Suppression Techniques for High-Speed Sample-and-Hold Circuits 2019 ·IEEE Transactions on Circuits and Systems I Regular Papers ·(unknown), Ramesh Harjani	4
16	High-Speed Circuits for a Multi-Lane 12 Gbps CMOS PRBS Generator 2007 ·(unknown), (unknown), Mahmood Ahmadi, Ramesh Harjani	3
17	Analysis and gain design of an integrated quadrature mixer with improved noise and image rejection. 2001 ·International Symposium on Circuits and Systems ·(unknown), Ramesh Harjani	1
18	A high speed low noise CMOS MR preamplifier for disk drives 1999 ·European Solid-State Circuits Conference ·(unknown), Ramesh Harjani	1
19	Macromodeling of analog circuits for hierarchical circuit design 1994 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·(unknown), Ramesh Harjani	6
20	Macrornodeling Of Analog Circuits For Hierarchical Circuit Design 1994 ·International Conference on Computer Aided Design ·(unknown), Ramesh Harjani	10

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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