John Wuu

433 total citations
14 papers, 253 citations indexed

About

John Wuu is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Networks and Communications. According to data from OpenAlex, John Wuu has authored 14 papers receiving a total of 253 indexed citations (citations by other indexed papers that have themselves been cited), including 10 papers in Hardware and Architecture, 8 papers in Electrical and Electronic Engineering and 5 papers in Computer Networks and Communications. Recurrent topics in John Wuu's work include Parallel Computing and Optimization Techniques (8 papers), Embedded Systems Design Techniques (6 papers) and Interconnection Networks and Systems (5 papers). John Wuu is often cited by papers focused on Parallel Computing and Optimization Techniques (8 papers), Embedded Systems Design Techniques (6 papers) and Interconnection Networks and Systems (5 papers). John Wuu collaborates with scholars based in United States, Canada and South Korea. John Wuu's co-authors include Raja Swaminathan, Rahul Agarwal, Patrick Cheng, Dave Johnson, Samuel Naffziger, Brett C. Johnson, Alan Smith, Chintan Patel, Hyun‐Jin Cho and W. Maszara and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Solid-State Circuits Magazine and 2022 IEEE International Solid- State Circuits Conference (ISSCC).

In The Last Decade

John Wuu

12 papers receiving 229 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
John Wuu United States	7	196	97	68	19	13	14	253
Norman Robson United States	12	269 1.4×	124 1.3×	38 0.6×	24 1.3×	9 0.7×	29	300
C.C. Liu United States	6	270 1.4×	152 1.6×	146 2.1×	30 1.6×	13 1.0×	10	342
Boris Vaisband United States	11	248 1.3×	46 0.5×	43 0.6×	14 0.7×	10 0.8×	42	270
P. Parries United States	10	230 1.2×	114 1.2×	95 1.4×	19 1.0×	4 0.3×	19	273
Hongjung Kim South Korea	7	274 1.4×	102 1.1×	86 1.3×	18 0.9×	20 1.5×	14	334
Mikhail Popovich United States	13	399 2.0×	54 0.6×	52 0.8×	33 1.7×	5 0.4×	27	417
Kwangok Jeong United States	13	347 1.8×	141 1.5×	41 0.6×	47 2.5×	5 0.4×	36	385
Fabrice Caignet France	11	363 1.9×	89 0.9×	46 0.7×	34 1.8×	6 0.5×	37	376
Robert Sankman United States	5	301 1.5×	79 0.8×	42 0.6×	54 2.8×	14 1.1×	8	336
Sukeshwar Kannan United States	12	328 1.7×	78 0.8×	25 0.4×	37 1.9×	31 2.4×	46	361

Countries citing papers authored by John Wuu

Since Specialization

Citations

This map shows the geographic impact of John Wuu's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by John Wuu with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites John Wuu more than expected).

Fields of papers citing papers by John Wuu

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by John Wuu. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by John Wuu. The network helps show where John Wuu may publish in the future.

Co-authorship network of co-authors of John Wuu

This figure shows the co-authorship network connecting the top 25 collaborators of John Wuu. A scholar is included among the top collaborators of John Wuu based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with John Wuu. John Wuu is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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14 of 14 papers shown

Kulkarni, Deepak V., et al.. (2024). Advancing AI with Energy-Efficient Architectures: Innovations in Fab Process, Packaging, and System Integration. 1–6.

Wuu, John, Mike Mantor, Gabriel H. Loh, et al.. (2024). Coevolution of Chiplet Technology and Cache Architecture for AI and Compute. 1–4. 2 indexed citations

Patel, Chintan, et al.. (2024). 11.1 AMD InstinctTM MI300 Series Modular Chiplet Package – HPC and AI Accelerator for Exa-Class Systems. 490–492. 14 indexed citations

Smith, Alan, et al.. (2024). AMD Instinct™ MI300X Accelerator: Packaging and Architecture Co-Optimization. 1–2. 2 indexed citations

Cheng, Patrick, et al.. (2024). 3.5D Advanced Packaging Enabling Heterogenous Integration of HPC and AI Accelerators. 798–802. 4 indexed citations

Chang, Tsung-Yung Jonathan, et al.. (2023). A Trip Down Memory Lane: Reflections on the progress in memories. IEEE Solid-State Circuits Magazine. 15(3). 53–61. 1 indexed citations

Wuu, John, Rahul Agarwal, Brett C. Johnson, et al.. (2022). 3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU. 2022 IEEE International Solid- State Circuits Conference (ISSCC). 428–429. 48 indexed citations

Agarwal, Rahul, et al.. (2022). 3D Packaging for Heterogeneous Integration. 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC). 1103–1107. 61 indexed citations

Wuu, John, et al.. (2011). An 8MB level-3 cache in 32nm SOI with column-select aliasing. 258–260. 5 indexed citations

10.

Gupta, Rajesh, et al.. (2010). 32nm high-density high-speed T-RAM embedded memory technology. 12.1.1–12.1.4. 18 indexed citations

11.

Wuu, John, et al.. (2009). A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology. 460–461,461a. 9 indexed citations

12.

Wuu, John, et al.. (2005). The asynchronous 24MB on-chip level-3 cache for a dual-core Itanium-family processor. 488–490. 33 indexed citations

13.

Wuu, John, et al.. (2002). The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor. IEEE Journal of Solid-State Circuits. 37(11). 1523–1529. 52 indexed citations

14.

Wuu, John, et al.. (2002). An on-chip 3MB subarray-based 3rd level cache on an itanium microprocessor. 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315). 88–413. 4 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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