John Wuu

433 citations

14 papers · 253 indexed · h-index 7

Impact in

Hardware and Architecture top 5%
- Parallel Computing and Optimization Techniques
Electrical and Electronic Engineering
- 3D IC and TSV technologies
- Semiconductor materials and devices
- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- Electronic Packaging and Soldering Technologies
- Advanced Memory and Neural Computing

Papers in ⓘ

Hardware and Architecture 10
- Parallel Computing and Optimization Techniques 8
- Embedded Systems Design Techniques 6
Computer Networks and Communications 5
- Interconnection Networks and Systems 5

Co-authors: Raja Swaminathan (6 shared papers)Rahul Agarwal (2 shared papers)Patrick Cheng (2 shared papers)Brett C. Johnson (2 shared papers)Samuel Naffziger (3 shared papers)Dave Johnson (2 shared papers)Alan Smith (3 shared papers)Nihar R. Mohapatra (1 shared paper)
Journals: IEEE Solid-State Circuits Magazine (1 paper)IEEE Journal of Solid-State Circuits (1 paper)2022 IEEE International Solid- State Circuits Conference (ISSCC) (1 paper)2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) (1 paper)2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) (1 paper)
Partner nations: United States Canada Taiwan

In The Last Decade

John Wuu

12 papers receiving 229 citations

Peers

Countries citing papers authored by John Wuu

Since Specialization

Citations

This map shows the geographic impact of John Wuu's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by John Wuu with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites John Wuu more than expected).

Fields of papers citing papers by John Wuu

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by John Wuu. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by John Wuu. The network helps show where John Wuu may publish in the future.

Co-authors

The 24 scholars most cited alongside John Wuu, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with John Wuu Line = papers co-authored together John Wuu links everyone, so they are left out of the graph.

All Works

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14 of 14 papers shown

#	Work
1	3D Packaging for Heterogeneous Integration 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) ·Rahul Agarwal, Patrick Cheng, Priyal Shah, Brett Wilkerson, Raja Swaminathan, John Wuu, Chandrasekhar Mandalapu	2022	61
2	The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor IEEE Journal of Solid-State Circuits ·D. Weiss, John Wuu, V. Chin	2002	52
3	3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU 2022 IEEE International Solid- State Circuits Conference (ISSCC) ·John Wuu, Rahul Agarwal, Michael Ciraula, Carl Dietz, Brett C. Johnson, Dave Johnson, Russell Schreiber, Raja Swaminathan, W. Laurens Walker, Samuel Naffziger	2022	48
4	The asynchronous 24MB on-chip level-3 cache for a dual-core Itanium-family processor John Wuu, D. Weiss, Charles Morganti, Michael Dreesen	2005	33
5	32nm high-density high-speed T-RAM embedded memory technology Rajesh Gupta, F. Nemati, Scott Robins, Kevin Yang, Vasudevan Gopalakrishnan, Joseph John Sundarraj, Rajesh Chopra, Rich Roy, Hyun‐Jin Cho, W. Maszara, Nihar R. Mohapatra, John Wuu, D. Weiss, Sam Nakib	2010	18
6	11.1 AMD InstinctTM MI300 Series Modular Chiplet Package – HPC and AI Accelerator for Exa-Class Systems A.J. Smith, Eric Chapman, Chintan Patel, Raja Swaminathan, John Wuu, Tyrone Huang, Wonjun Jung, Alexander Kaganov, H. McIntyre, R. Mangaser	2024	14
7	A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology A.P. Singh, Michael Ciraula, D. Weiss, John Wuu, P. Bauser, P. de Champs, H. Daghighian, David Fisch, P. Graber, Morgan Bron	2009	9
8	An 8MB level-3 cache in 32nm SOI with column-select aliasing D. Weiss, Michael Dreesen, Michael Ciraula, Carson Henrion, Chris Helt, Ryan Freese, Tommy Miles, Anita Karegar, Russell Schreiber, Bryan Schneller, John Wuu	2011	5
9	3.5D Advanced Packaging Enabling Heterogenous Integration of HPC and AI Accelerators Chandra Sekhar Mandalapu, Chintan Buch, Priyal Shah, Roden Topacio, Patrick Cheng, Liwei Wang, Raja Swaminathan, Alan Smith, John Wuu, Kaushik Mysore, Arsalan Alam	2024	4
10	An on-chip 3MB subarray-based 3rd level cache on an itanium microprocessor 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) ·D. Weiss, John Wuu, V. Chin	2002	4
11	Coevolution of Chiplet Technology and Cache Architecture for AI and Compute John Wuu, Mike Mantor, Gabriel H. Loh, Alan Smith, Dave Johnson, David G. Fisher, Brett C. Johnson, Carson Henrion, Russell Schreiber, Jeff Lucas, Stephen Dussinger, Andy Tomlinson, W. Laurens Walker, Paula Moyer, Deepak Kulkarni, Daniel Ng, Wonjun Jung, Raja Swaminathan, Samuel Naffziger	2024	2
12	AMD Instinct™ MI300X Accelerator: Packaging and Architecture Co-Optimization Alan Smith, Gabriel H. Loh, John Wuu, Samuel Naffziger, Tyrone Huang, H. McIntyre, R. Mangaser, Wonjun Jung, Raja Swaminathan	2024	2
13	A Trip Down Memory Lane: Reflections on the progress in memories IEEE Solid-State Circuits Magazine ·Tsung-Yung Jonathan Chang, Fatih Hamzaoglu, Yan Li, Kyomin Sohn, Yuxiao Wang, John Wuu	2023	1
14	Advancing AI with Energy-Efficient Architectures: Innovations in Fab Process, Packaging, and System Integration M. Fuselier, L.A. Bair, Deepak V. Kulkarni, Gamal Refai-Ahmed, John Wuu, Omar Zia	2024	0

About John Wuu

John Wuu is a scholar working on Hardware and Architecture, Computer Networks and Communications, Electrical and Electronic Engineering, Automotive Engineering and Cellular and Molecular Neuroscience, having authored 14 papers that have together received 253 indexed citations. Recurring topics across this work include Parallel Computing and Optimization Techniques (8 papers), Embedded Systems Design Techniques (6 papers), Interconnection Networks and Systems (5 papers), Semiconductor materials and devices (3 papers), Advanced Memory and Neural Computing (3 papers), Low-power high-performance VLSI design (2 papers), 3D IC and TSV technologies (2 papers) and Neuroscience and Neural Engineering (1 paper). The work is most often cited by research in Hardware and Architecture (97 citations), Electrical and Electronic Engineering (196 citations), Computer Networks and Communications (68 citations), Automotive Engineering (13 citations) and Industrial and Manufacturing Engineering (5 citations). John Wuu has collaborated with scholars based in United States, Canada and Taiwan. Frequent co-authors include Raja Swaminathan, Rahul Agarwal, Patrick Cheng, Brett C. Johnson, Samuel Naffziger, Dave Johnson, Alan Smith, Nihar R. Mohapatra, Rajesh Gupta and W. Maszara. Their work appears in journals such as IEEE Solid-State Circuits Magazine, IEEE Journal of Solid-State Circuits, 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) and 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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