S. Aur

762 total citations
36 papers, 383 citations indexed

About

S. Aur is a scholar working on Electrical and Electronic Engineering, Condensed Matter Physics and Mechanics of Materials. According to data from OpenAlex, S. Aur has authored 36 papers receiving a total of 383 indexed citations (citations by other indexed papers that have themselves been cited), including 36 papers in Electrical and Electronic Engineering, 1 paper in Condensed Matter Physics and 1 paper in Mechanics of Materials. Recurrent topics in S. Aur's work include Semiconductor materials and devices (36 papers), Advancements in Semiconductor Devices and Circuit Design (30 papers) and Integrated Circuits and Semiconductor Failure Analysis (16 papers). S. Aur is often cited by papers focused on Semiconductor materials and devices (36 papers), Advancements in Semiconductor Devices and Circuit Design (30 papers) and Integrated Circuits and Semiconductor Failure Analysis (16 papers). S. Aur collaborates with scholars based in United States. S. Aur's co-authors include Amitava Chatterjee, T. Polgreen, M. Rödder, A. Amerasekera, Ping Yang, Paul E. Nicollian, S. Krishnan, D.E. Hocevar, S. Rangan and I.-C. Chen and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Electron Devices and IEEE Electron Device Letters.

In The Last Decade

S. Aur

35 papers receiving 355 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
S. Aur United States 13 376 32 27 15 15 36 383
S. Rangan United States 7 322 0.9× 19 0.6× 19 0.7× 16 1.1× 22 1.5× 12 323
Tomasz Brożek United States 9 273 0.7× 26 0.8× 48 1.8× 19 1.3× 10 0.7× 76 292
Andreas Martin Germany 12 501 1.3× 54 1.7× 35 1.3× 21 1.4× 35 2.3× 72 519
H. Katto Japan 10 255 0.7× 16 0.5× 19 0.7× 36 2.4× 10 0.7× 34 262
J.D. Hayden United States 9 318 0.8× 10 0.3× 35 1.3× 29 1.9× 13 0.9× 34 326
R. Bolam United States 9 244 0.6× 39 1.2× 20 0.7× 12 0.8× 18 1.2× 30 249
Paul E. Nicollian United States 14 585 1.6× 41 1.3× 64 2.4× 32 2.1× 21 1.4× 29 591
S. Mittl United States 12 285 0.8× 22 0.7× 16 0.6× 7 0.5× 8 0.5× 28 292
S. C. Song United States 9 268 0.7× 19 0.6× 39 1.4× 32 2.1× 7 0.5× 37 280
P. O'Sullivan Ireland 8 256 0.7× 18 0.6× 25 0.9× 35 2.3× 7 0.5× 42 276

Countries citing papers authored by S. Aur

Since Specialization
Citations

This map shows the geographic impact of S. Aur's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by S. Aur with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites S. Aur more than expected).

Fields of papers citing papers by S. Aur

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by S. Aur. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by S. Aur. The network helps show where S. Aur may publish in the future.

Co-authorship network of co-authors of S. Aur

This figure shows the co-authorship network connecting the top 25 collaborators of S. Aur. A scholar is included among the top collaborators of S. Aur based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with S. Aur. S. Aur is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Aur, S., et al.. (2005). MOSFET asymmetry and gate-drain/source overlap effects on hot carrier reliability. 714–715. 1 indexed citations
2.
Aur, S.. (2003). Kinetics of hot carrier effects for circuit simulation. 88–91. 4 indexed citations
3.
Hu, Jianghai, et al.. (2003). A 1.2V, sub-0.09 μm gate length CMOS technology. 419–422. 7 indexed citations
4.
Shanware, A., M. R. Visokay, Antonio Rotondaro, et al.. (2003). Evaluation of the positive biased temperature stress stability in HfSiON gate dielectrics. 208–213. 20 indexed citations
5.
Krishnan, S., et al.. (2002). High density plasma etch induced damage to thin gate oxide. 315–318. 9 indexed citations
6.
Kraft, R., Siddarth Krishnan, Bruce K. Gale, et al.. (2002). A comprehensive assessment of microtrenching during high density polysilicon etch. 84–87. 1 indexed citations
7.
Rödder, M., S. V. Hattangady, Ning Yu, et al.. (2002). A 1.2 V, 0.1 μm gate length CMOS technology: design and process issues. 623–626. 15 indexed citations
8.
Rödder, M., et al.. (2002). Oxide thickness dependence of inverter delay and device reliability for 0.25 μm CMOS technology. cad 1. 879–882. 2 indexed citations
9.
Hong, Q. Z., et al.. (2002). A sub-0.1 μm gate length CMOS technology for high performance (1.5 V) and low power (1.0 V). 563–566. 9 indexed citations
10.
Krishnan, S., A. Amerasekera, S. Rangan, & S. Aur. (2002). Antenna device reliability for ULSI processing. 601–604. 23 indexed citations
11.
Nag, Soumya Shubhra, et al.. (2002). Comparative evaluation of gap-fill dielectrics in shallow trench isolation for sub-0.25 μm technologies. 841–845. 11 indexed citations
12.
Chatterjee, Amitava, et al.. (2002). Pass transistor designs using pocket implant to improve manufacturability for 256 Mbit DRAM and beyond. 87–90. 5 indexed citations
13.
Rödder, M., et al.. (2002). A study of design/process dependence of 0.25 μm gate length CMOS. 71–74. 1 indexed citations
14.
Krishnan, S., et al.. (2002). Inductively coupled plasma (ICP) metal etch damage to 35-60 A gate oxide. 731–734. 9 indexed citations
15.
Chatterjee, P.K., W. R. Hunter, A. Amerasekera, et al.. (1995). Trends for deep submicron VLSI and their implications for reliability. 1–11. 39 indexed citations
16.
Aur, S., C. Duvvury, H. McAdams, & C. Perrin. (1992). Identification of DRAM sense-amplifier imbalance using hot-carrier evaluation. IEEE Journal of Solid-State Circuits. 27(3). 451–453. 1 indexed citations
17.
Aur, S. & Amitava Chatterjee. (1990). On the robustness of LDD nMOS transistors subjected to measurement of drain breakdown voltage. Solid-State Electronics. 33(8). 1043–1048. 3 indexed citations
18.
Aur, S., Amitava Chatterjee, & T. Polgreen. (1988). Hot Electron Reliability and ESD Latent Damage. Reliability physics. 15–18. 14 indexed citations
19.
Aur, S., D.E. Hocevar, & Ping Yang. (1987). Circuit hot electron effect simulation. 498–501. 31 indexed citations
20.
Aur, S., Ping Yang, Pratap Pattnaik, & P.K. Chatterjee. (1985). Modeling of Hot Carrier Effects for LDD MOSFETs. Symposium on VLSI Technology. 112–113. 3 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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