David J. Garrod
- Electrical and Electronic Engineering top 10%
- Hardware and Architecture top 2%
- Biomedical Engineering
- Industrial and Manufacturing Engineering
- Computer Networks and Communications
- Topics
- VLSI and FPGA Design Techniques (7 papers)VLSI and Analog Circuit Testing (6 papers)3D IC and TSV technologies (4 papers)
- Cited by
- Hardware and ArchitectureElectrical and Electronic EngineeringIndustrial and Manufacturing Engineering
- Journals
- IEEE Journal of Solid-State Circuits
- Partner nations
- United States
In The Last Decade
David J. Garrod
7 papers receiving 436 citations
Peers
Comparison fields: 5 of 14
- Electrical and Electronic Engineering 439
- Hardware and Architecture 338
- Biomedical Engineering 24
- Industrial and Manufacturing Engineering 23
- Computer Networks and Communications 18
Countries citing papers authored by David J. Garrod
This map shows the geographic impact of David J. Garrod's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by David J. Garrod with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites David J. Garrod more than expected).
Fields of papers citing papers by David J. Garrod
This network shows the impact of papers produced by David J. Garrod. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by David J. Garrod. The network helps show where David J. Garrod may publish in the future.
Co-authorship network of co-authors of David J. Garrod
This figure shows the co-authorship network connecting the top 25 collaborators of David J. Garrod. A scholar is included among the top collaborators of David J. Garrod based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with David J. Garrod. David J. Garrod is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 17 | |
| 2 | 4 | |
| 3 | 6 | |
| 4 | 116 | |
| 5 | KOAN/ANAGRAM 11: New Tools for Device-Level Analog Placement and Routing | 30 |
| 6 | 254 | |
| 7 | 26 |
About David J. Garrod
David J. Garrod is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computational Theory and Mathematics, having authored 7 papers that have together received 453 indexed citations. Recurring topics across this work include VLSI and FPGA Design Techniques (7 papers), VLSI and Analog Circuit Testing (6 papers) and 3D IC and TSV technologies (4 papers). The work is most often cited by research in Hardware and Architecture (338 citations), Electrical and Electronic Engineering (439 citations) and Industrial and Manufacturing Engineering (23 citations). David J. Garrod has collaborated with scholars based in United States. Frequent co-authors include L.R. Carley, Rob A. Rutenbar, John M. Cohn, Emil S. Ochotta, John W. Kelly and Ramesh Harjani. Their work appears in journals such as IEEE Journal of Solid-State Circuits.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.