K. Furuta

508 total citations
16 papers, 280 citations indexed

About

K. Furuta is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Hardware and Architecture. According to data from OpenAlex, K. Furuta has authored 16 papers receiving a total of 280 indexed citations (citations by other indexed papers that have themselves been cited), including 12 papers in Electrical and Electronic Engineering, 6 papers in Biomedical Engineering and 4 papers in Hardware and Architecture. Recurrent topics in K. Furuta's work include Low-power high-performance VLSI design (6 papers), Advancements in PLL and VCO Technologies (6 papers) and Analog and Mixed-Signal Circuit Design (5 papers). K. Furuta is often cited by papers focused on Low-power high-performance VLSI design (6 papers), Advancements in PLL and VCO Technologies (6 papers) and Analog and Mixed-Signal Circuit Design (5 papers). K. Furuta collaborates with scholars based in Japan. K. Furuta's co-authors include M. Yamashina, Masayuki Mizuno, H. Abiko, Kohki Okabe, A. Ono, H. Yamada, Yasuhiro Nakazawa, Takayoshi Fujii, Masato Motomura and Katsunori Wakabayashi and has published in prestigious journals such as IEEE Journal of Solid-State Circuits and IEICE Transactions on Electronics.

In The Last Decade

K. Furuta

12 papers receiving 256 citations

Author Peers

Peers are selected by citation overlap in the author's most active subfields. citations · hero ref

Author						Papers	Cites
K. Furuta	206	94	64	55	44	16	280
M. Hamada	180 0.9×	90 1.0×	34 0.5×	116 2.1×	53 1.2×	9	282
M. Kanazawa	294 1.4×	127 1.4×	53 0.8×	37 0.7×	51 1.2×	10	329
T. Terazawa	240 1.2×	136 1.4×	42 0.7×	131 2.4×	75 1.7×	11	363
K. Suzuki	265 1.3×	84 0.9×	83 1.3×	25 0.5×	42 1.0×	9	300
M. Igarashi	485 2.4×	196 2.1×	108 1.7×	45 0.8×	96 2.2×	12	527
T. Takayanagi	167 0.8×	100 1.1×	17 0.3×	77 1.4×	55 1.3×	19	266
Uming Ko	395 1.9×	158 1.7×	117 1.8×	18 0.3×	58 1.3×	20	438
H. Mair	256 1.2×	87 0.9×	93 1.5×	15 0.3×	37 0.8×	7	280
S. Ramprasad	297 1.4×	175 1.9×	47 0.7×	30 0.5×	156 3.5×	13	331
Gary Yeap	267 1.3×	143 1.5×	46 0.7×	16 0.3×	45 1.0×	13	308

Countries citing papers authored by K. Furuta

Since Specialization

Citations

This map shows the geographic impact of K. Furuta's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by K. Furuta with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites K. Furuta more than expected).

Fields of papers citing papers by K. Furuta

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by K. Furuta. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by K. Furuta. The network helps show where K. Furuta may publish in the future.

Co-authorship network of co-authors of K. Furuta

This figure shows the co-authorship network connecting the top 25 collaborators of K. Furuta. A scholar is included among the top collaborators of K. Furuta based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with K. Furuta. K. Furuta is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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16 of 16 papers shown

Mizuno, Masayuki, M. Yamashina, K. Furuta, et al.. (2005). A Ghz Mos Adaptive Pipeline Technique Using Variable Delay Circuits. e75 c. 27–28. 1 indexed citations

Fujii, Takayoshi, K. Furuta, Masato Motomura, et al.. (2003). A dynamically reconfigurable logic engine with a multi-context/multi-mode unified-cell architecture. 364–365. 32 indexed citations

Furuta, K., Hiroshi Itô, Hitoshi Wakabayashi, et al.. (2002). A 0.9 V 100 MHz 4 mW 2 mm/sup 2/ 16 b DSP core. 84–85,.

Mizuno, Masayuki, K. Furuta, A. Tanabe, et al.. (2002). A 0.18 μm CMOS hot-standby phase-locked loop using a noise-immune adaptive-gain voltage-controlled oscillator. 268–269,. 6 indexed citations

Mizuno, Masayuki, K. Furuta, Yasuhiro Nakazawa, et al.. (2002). A 1.5 W single-chip MPEG2 MP@ML encoder with low power motion estimation and clocking. 256–257,. 12 indexed citations

Furuta, K., Takayoshi Fujii, Masato Motomura, Katsunori Wakabayashi, & M. Yamashina. (2002). Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI. 151–154. 11 indexed citations

Amano, H., et al.. (2002). A virtual hardware system on a dynamically reconfigurable logic device. 295–296. 6 indexed citations

Yamashina, M., Masayuki Mizuno, K. Furuta, et al.. (2002). A low-supply voltage GHz MOS integrated circuit for mobile computing systems. e75 c. 80–81.

Mizuno, Masayuki, et al.. (2002). Elastic-Vt CMOS circuits for multiple on-chip power control. 300–301,. 5 indexed citations

10.

Mizuno, Masayuki, et al.. (1997). A 0.18-µm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCO. IEICE Transactions on Electronics. 80(12). 1560–1571.

11.

Furuta, K., Hiroshi Itô, Hitoshi Wakabayashi, et al.. (1997). A 0.25-μm CMOS 0.9-V 100-MHz DSP core. IEEE Journal of Solid-State Circuits. 32(1). 52–61. 27 indexed citations

12.

Mizuno, Masayuki, K. Furuta, A. Shibayama, et al.. (1997). A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking. IEEE Journal of Solid-State Circuits. 32(11). 1807–1816. 51 indexed citations

13.

Mizuno, Masayuki, M. Yamashina, K. Furuta, et al.. (1996). A GHz MOS adaptive pipeline technique using MOS current-mode logic. IEEE Journal of Solid-State Circuits. 31(6). 784–791. 93 indexed citations

14.

Furuta, K., Hiroshi Ito, Hitoshi Wakabayashi, et al.. (1995). A 0.25μm CMOS 0.9V 100MHz DSP Core. 95(20). 1–7. 1 indexed citations

15.

Nakamura, Kentaro, et al.. (1990). A 5 ns 1 Mb ECL BiCMOS SRAM. 138–139. 14 indexed citations

16.

Nakamura, Kazuyuki, et al.. (1990). A 5-ns 1-Mb ECL BiCMOS SRAM. IEEE Journal of Solid-State Circuits. 25(5). 1057–1062. 21 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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