Chunlei Wu

949 citations

39 papers · 641 indexed · h-index 14

Co-authors: Ru Huang Qianqian Huang Yangyuan Wang Jiaxin WangCheng ChenZhan ZhanChao WangWenzhe Jiang
Topics: Semiconductor materials and devices (33 papers)Advancements in Semiconductor Devices and Circuit Design (27 papers)Integrated Circuits and Semiconductor Failure Analysis (9 papers)
Cited by: Electrical and Electronic Engineering Condensed Matter Physics Biomedical Engineering
Journals: Journal of Applied Physics IEEE Access IEEE Transactions on Electron Devices
Partner nations: China United States Türkiye

In The Last Decade

Chunlei Wu

36 papers receiving 618 citations

Peers

Countries citing papers authored by Chunlei Wu

Since Specialization

Citations

This map shows the geographic impact of Chunlei Wu's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Chunlei Wu with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Chunlei Wu more than expected).

Fields of papers citing papers by Chunlei Wu

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Chunlei Wu. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Chunlei Wu. The network helps show where Chunlei Wu may publish in the future.

Co-authorship network of co-authors of Chunlei Wu

This figure shows the co-authorship network connecting the top 25 collaborators of Chunlei Wu. A scholar is included among the top collaborators of Chunlei Wu based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Chunlei Wu. Chunlei Wu is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	A Novel Hybrid-Channel Gate-All-Around Nanosheet Transistor for Leakage Control and Subthreshold Slope Reduction 2024 ·(unknown),Chunlei Wu,(unknown),(unknown),(unknown),(unknown),Dawei Wang,Tao Liu,David Wei Zhang	0
2	A Buried Thermal Rail (BTR) Technology to Improve Electrothermal Characteristics of Complementary Field-Effect Transistor (CFET) 2023 ·Micromachines ·(unknown),Tao Liu,Jingwen Yang,(unknown),(unknown),Chunlei Wu,Min Xu,David Wei Zhang	2
3	Investigation of Source/Drain Recess Engineering and Its Impacts on FinFET and GAA Nanosheet FET at 5 nm Node 2023 ·Electronics ·Dawei Wang,(unknown),Tao Liu,(unknown),Jingwen Yang,Chunlei Wu,Min Xu,(unknown)	13
4	A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors 2023 ·Micromachines ·Jingwen Yang,(unknown),Dawei Wang,Tao Liu,(unknown),(unknown),(unknown),(unknown),(unknown),Chunlei Wu,Min Xu,David Wei Zhang	5
5	Strained Si Nanosheet pFET Based on SiC Strain Relaxed Buffer Layer for High Performance and Low Power Logic Applications 2023 ·IEEE Access ·(unknown),(unknown),Chunlei Wu,Chen Wang,Min Xu,David Wei Zhang	1
6	Impact of Stress and Dimension on Nanosheet Deformation during Channel Release of Gate-All-Around Device 2023 ·Micromachines ·Jingwen Yang,(unknown),Dawei Wang,Tao Liu,(unknown),Qiang Wang,(unknown),(unknown),(unknown),Chen Wang,Chunlei Wu,Min Xu,David Wei Zhang	5
7	A Novel Si Nanosheet Channel Release Process for the Fabrication of Gate-All-Around Transistors and Its Mechanism Investigation 2023 ·Nanomaterials ·(unknown),Dawei Wang,(unknown),Tao Liu,Jingwen Yang,Kun Chen,Luyu Wang,(unknown),Min Xu,Chen Wang,Chunlei Wu,(unknown),David Wei Zhang	9
8	Ferroelectric-Gated GaN HEMTs for RF and mm-Wave Switch Applications 2022 ·(unknown),Chunlei Wu,(unknown),Jingshan Wang,Yu Cao,(unknown),Edward Beam,Patrick Fay	6
9	Investigation of Nanosheet Deformation During Channel-Release in Gate-All-Around Nanosheet Transistors 2022 ·Jingwen Yang,Kun Chen,(unknown),Dawei Wang,Qiang Wang,(unknown),(unknown),(unknown),(unknown),Chunlei Wu,Min Xu,David Wei Zhang	1
10	High Selectivity, Low Damage ICP Etching of p-GaN over AlGaN for Normally-off p-GaN HEMTs Application 2022 ·Micromachines ·Penghao Zhang,Luyu Wang,(unknown),(unknown),Rong Fan,(unknown),(unknown),Min Xu,Chen Wang,Chunlei Wu,David Zhang	16
11	Study of Synthetic Electric Field Effects and Quantum Confinement Effects in Extremely Scaled Gate-All-Around Tunnel FET 2022 ·(unknown),(unknown),Dawei Wang,Tao Liu,Jingwen Yang,Kun Chen,(unknown),Chunlei Wu,Min Xu,David Wei Zhang	4
12	Source/Drain Trimming Process to Improve Gate-All-Around Nanosheet Transistors Switching Performance and Enable More Stacks of Nanosheets 2022 ·Micromachines ·(unknown),Jingwen Yang,Tao Liu,Dawei Wang,Min Xu,Chunlei Wu,Chen Wang,(unknown),David Wei Zhang,Wenchao Liu	2
13	Novel Postgate Single Diffusion Break Integration in Gate-All-Around Nanosheet Transistors to Achieve Remarkable Channel Stress for N/P Current Matching 2022 ·IEEE Transactions on Electron Devices ·Tao Liu,Dawei Wang,(unknown),(unknown),Jingwen Yang,Chunlei Wu,(unknown),Chen Wang,Min Xu,David Wei Zhang	8
14	Hf_0.5Zr_0.5O₂-Based Ferroelectric Gate HEMTs With Large Threshold Voltage Tuning Range 2020 ·IEEE Electron Device Letters ·Chunlei Wu,(unknown),(unknown),J. A. Smith,Benjamin Grisafe,Suman Datta,Patrick Fay	40
15	A Novel Tunnel FET Design Through Adaptive Bandgap Engineering With Constant Sub-Threshold Slope Over 5 Decades of Current and High $\text{I}_{\mathrm {ON}}/\text{I}_{\mathrm {OFF}}$ Ratio 2017 ·IEEE Electron Device Letters ·(unknown),Chunlei Wu,Qianqian Huang,Cheng Chen,Jiadi Zhu,(unknown),Rundong Jia,(unknown),Yuchao Yang,Ming Li,Ru Huang	42
16	Design and Simulation of a Novel Graded-Channel Heterojunction Tunnel FET With High ${I} _{\scriptscriptstyle\text {ON}}/{I} _{\scriptscriptstyle\text {OFF}}$ Ratio and Steep Swing 2017 ·IEEE Electron Device Letters ·Jiadi Zhu,(unknown),Qianqian Huang,Cheng Chen,Chunlei Wu,Rundong Jia,Ru Huang	30
17	High performance tunnel field-effect transistor by gate and source engineering 2014 ·Nanotechnology ·Ru Huang,Qianqian Huang,Shaowen Chen,Chunlei Wu,Jiaxin Wang,Xia An,Yangyuan Wang	14
18	Influence of NixMn1−x thickness and composition on the Curie temperature of Ni in NixMn1−x/Ni bilayers on Cu3Au(001) 2014 ·Journal of Magnetism and Magnetic Materials ·Mustafa Erkovan,(unknown),(unknown),Chunlei Wu,W. Kuch	6
19	A novel Si tunnel FET with 36mV/dec subthreshold slope based on junction depleted-modulation through striped gate configuration 2012 ·Qianqian Huang,Ru Huang,Zhan Zhan,(unknown),Wenzhe Jiang,Chunlei Wu,Yangyuan Wang	109
20	Transverse Dimensions of Wood Pulp Fibres and Their Implications for End Use 1997 ·R. S. Seth,(unknown),B. K. Chan,Chunlei Wu	2

About Chunlei Wu

Chunlei Wu is a scholar working on Architecture, Electrical and Electronic Engineering and Condensed Matter Physics, having authored 39 papers that have together received 641 indexed citations. Recurring topics across this work include Semiconductor materials and devices (33 papers), Advancements in Semiconductor Devices and Circuit Design (27 papers) and Integrated Circuits and Semiconductor Failure Analysis (9 papers). The work is most often cited by research in Electrical and Electronic Engineering (601 citations), Condensed Matter Physics (58 citations) and Biomedical Engineering (155 citations). Chunlei Wu has collaborated with scholars based in China, United States and Türkiye. Frequent co-authors include Ru Huang, Qianqian Huang, Yangyuan Wang, Jiaxin Wang, Cheng Chen, Zhan Zhan, Chao Wang, Wenzhe Jiang, Rundong Jia and Patrick Fay. Their work appears in journals such as Journal of Applied Physics, IEEE Access and IEEE Transactions on Electron Devices.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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