Ching-Chao Huang

618 total citations
26 papers, 489 citations indexed

About

Ching-Chao Huang is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, Ching-Chao Huang has authored 26 papers receiving a total of 489 indexed citations (citations by other indexed papers that have themselves been cited), including 24 papers in Electrical and Electronic Engineering, 3 papers in Hardware and Architecture and 3 papers in Biomedical Engineering. Recurrent topics in Ching-Chao Huang's work include Electromagnetic Compatibility and Noise Suppression (12 papers), 3D IC and TSV technologies (8 papers) and Low-power high-performance VLSI design (7 papers). Ching-Chao Huang is often cited by papers focused on Electromagnetic Compatibility and Noise Suppression (12 papers), 3D IC and TSV technologies (8 papers) and Low-power high-performance VLSI design (7 papers). Ching-Chao Huang collaborates with scholars based in United States. Ching-Chao Huang's co-authors include S. Ramesh, E.P. Giannelis, Kevin Donnelly, Jie Gao, Mark Horowitz, S. Sidiropoulos, D. Stark, J. Wei, Jared Zerbe and B.W. Garlepp and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Microwave Theory and Techniques and IBM Journal of Research and Development.

In The Last Decade

Ching-Chao Huang

25 papers receiving 461 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Ching-Chao Huang United States	9	385	246	99	47	30	26	489
Rupendra Kumar Sharma Czechia	14	539 1.4×	78 0.3×	57 0.6×	89 1.9×	15 0.5×	42	578
N. Srivastava United States	7	454 1.2×	76 0.3×	364 3.7×	29 0.6×	40 1.3×	9	570
L. Shi United States	9	487 1.3×	112 0.5×	36 0.4×	11 0.2×	22 0.7×	13	512
Hyunwoong Kim South Korea	8	271 0.7×	68 0.3×	34 0.3×	10 0.2×	13 0.4×	32	314
Laurent Brunet France	10	277 0.7×	78 0.3×	56 0.6×	22 0.5×	9 0.3×	51	368
Ki-Hyun Yoon South Korea	8	340 0.9×	28 0.1×	80 0.8×	15 0.3×	39 1.3×	12	367
M.M. Jevtić Serbia	10	264 0.7×	69 0.3×	91 0.9×	9 0.2×	8 0.3×	55	305
D.L. Kencke United States	13	364 0.9×	35 0.1×	159 1.6×	20 0.4×	35 1.2×	34	423
J. Mason United States	7	410 1.1×	49 0.2×	186 1.9×	19 0.4×	34 1.1×	15	439
Mark Jacunski United States	6	413 1.1×	48 0.2×	99 1.0×	10 0.2×	6 0.2×	16	435

Countries citing papers authored by Ching-Chao Huang

Since Specialization

Citations

This map shows the geographic impact of Ching-Chao Huang's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Ching-Chao Huang with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Ching-Chao Huang more than expected).

Fields of papers citing papers by Ching-Chao Huang

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Ching-Chao Huang. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Ching-Chao Huang. The network helps show where Ching-Chao Huang may publish in the future.

Co-authorship network of co-authors of Ching-Chao Huang

This figure shows the co-authorship network connecting the top 25 collaborators of Ching-Chao Huang. A scholar is included among the top collaborators of Ching-Chao Huang based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Ching-Chao Huang. Ching-Chao Huang is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

1.

Huang, Ching-Chao, et al.. (2014). Minimizing differential crosstalk of vias for high-speed data transmission. 191–194. 14 indexed citations

2.

Huang, Ching-Chao, et al.. (2005). Accurate analysis of multi-layered signal and power distributions using the fringe RLGC models. Electrical Performance of Electronic Packaging. 103–106. 7 indexed citations

3.

Burton, Scott, et al.. (2005). The effect of edge metal profiles on the accuracy of electrical modeling of advanced packages. IEEE Transactions on Advanced Packaging. 28(4). 720–723. 1 indexed citations

4.

Huang, Ching-Chao, et al.. (2003). Design and characterization of a high-performance wire-bond ball-grid-array package. 245–249. 1 indexed citations

5.

Wei, J., et al.. (2003). A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs. 88–91. 19 indexed citations

6.

Oh, Kyung Suk & Ching-Chao Huang. (2003). Efficient representation of multi-bit data bus structures by symmetric two-line models. Electrical Performance of Electronic Packaging. 19. 141–144. 1 indexed citations

7.

Huang, Ching-Chao, et al.. (2003). Physical layer design of a 1.6 GB/s DRAM bus. 11–14. 5 indexed citations

8.

Ramesh, S., et al.. (2003). Integrated thin film capacitors: interfacial control and implications on fabrication and performance. 99–104. 8 indexed citations

9.

Huang, Ching-Chao, et al.. (2003). RDRAM/spl reg/ channel design with 32-bit 4.8 GB/s memory modules. Electrical Performance of Electronic Packaging. 19–22. 3 indexed citations

10.

Feng, Jun‐e & Ching-Chao Huang. (2003). Equivalent driver model for fast system simulation. 264–266. 2 indexed citations

11.

Huang, Ching-Chao, et al.. (2002). RDRAM@ Channel Design with 32-bit 4.8GB/s Memory Modules. 3 indexed citations

12.

Beyene, W.T., et al.. (2002). Design and verification of differential transmission lines. 85–88. 17 indexed citations

13.

Huang, Ching-Chao, et al.. (2002). Model extraction and waveform correlation via a generalized frequency- and time-domain optimizer. 141–144. 1 indexed citations

14.

Huang, Ching-Chao & J.-H. Chern. (2002). Accurate modeling of capacitive, resistive and inductive effects of interconnect. 18. 115–115. 2 indexed citations

15.

Donnelly, Kevin, Samir Patel, Brian Lau, et al.. (2002). A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC. 290–291,.

16.

Huang, Ching-Chao, et al.. (2002). Improving the accuracy of on-chip parasitic extraction. Electrical Performance of Electronic Packaging. 42–45. 5 indexed citations

17.

Huang, Ching-Chao & Jiagui Feng. (2002). Optimizing VNA measurements by cascaded transmission lines for interconnect characterization. 107–110. 2 indexed citations

18.

Garlepp, B.W., Kevin Donnelly, Jun Kim, et al.. (2002). A portable digital DLL architecture for CMOS interface circuits. 214–215. 9 indexed citations

19.

Huang, Ching-Chao. (1994). Two-dimensional capacitance calculation in stratified and/or arbitrary dielectric media. IEEE Transactions on Microwave Theory and Techniques. 42(3). 501–504. 6 indexed citations

20.

Huang, Ching-Chao & Leon Wu. (1987). Signal degradation through module pins in VLSI packaging. IBM Journal of Research and Development. 31(4). 489–498. 17 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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