Ben Keller

1.4k total citations
28 papers, 941 citations indexed

About

Ben Keller is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Vision and Pattern Recognition. According to data from OpenAlex, Ben Keller has authored 28 papers receiving a total of 941 indexed citations (citations by other indexed papers that have themselves been cited), including 25 papers in Electrical and Electronic Engineering, 13 papers in Hardware and Architecture and 8 papers in Computer Vision and Pattern Recognition. Recurrent topics in Ben Keller's work include Low-power high-performance VLSI design (15 papers), Parallel Computing and Optimization Techniques (8 papers) and Advanced Neural Network Applications (8 papers). Ben Keller is often cited by papers focused on Low-power high-performance VLSI design (15 papers), Parallel Computing and Optimization Techniques (8 papers) and Advanced Neural Network Applications (8 papers). Ben Keller collaborates with scholars based in United States, France and United Kingdom. Ben Keller's co-authors include Brucek Khailany, Brian Zimmer, William J. Dally, Rangharajan Venkatesan, Matthew Fojtik, Yanqing Zhang, Alicia Klinefelter, Stephen G. Tell, C. Thomas Gray and Nathaniel Pinckney and has published in prestigious journals such as Communications of the ACM, IEEE Journal of Solid-State Circuits and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In The Last Decade

Ben Keller

27 papers receiving 915 citations

Author Peers

Peers are selected by citation overlap in the author's most active subfields. citations · hero ref

Author Last Decade Papers Cites
Ben Keller 660 385 232 163 154 28 941
Brian Zimmer 845 1.3× 416 1.1× 262 1.1× 195 1.2× 188 1.2× 49 1.2k
C. Thomas Gray 864 1.3× 350 0.9× 196 0.8× 181 1.1× 144 0.9× 55 1.1k
Stephen G. Tell 628 1.0× 302 0.8× 191 0.8× 197 1.2× 155 1.0× 41 934
Matthew Fojtik 1.0k 1.6× 485 1.3× 223 1.0× 253 1.6× 123 0.8× 32 1.3k
Nathaniel Pinckney 1.0k 1.5× 484 1.3× 253 1.1× 236 1.4× 196 1.3× 44 1.4k
Jaeha Kung 536 0.8× 223 0.6× 305 1.3× 144 0.9× 230 1.5× 51 827
Sae Kyu Lee 872 1.3× 281 0.7× 410 1.8× 127 0.8× 379 2.5× 22 1.2k
Paul N. Whatmough 577 0.9× 243 0.6× 294 1.3× 151 0.9× 216 1.4× 32 879
Farhana Sheikh 616 0.9× 309 0.8× 185 0.8× 149 0.9× 201 1.3× 47 899
Andrea Calimera 762 1.2× 224 0.6× 115 0.5× 88 0.5× 96 0.6× 116 957

Countries citing papers authored by Ben Keller

Since Specialization
Citations

This map shows the geographic impact of Ben Keller's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Ben Keller with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Ben Keller more than expected).

Fields of papers citing papers by Ben Keller

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Ben Keller. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Ben Keller. The network helps show where Ben Keller may publish in the future.

Co-authorship network of co-authors of Ben Keller

This figure shows the co-authorship network connecting the top 25 collaborators of Ben Keller. A scholar is included among the top collaborators of Ben Keller based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Ben Keller. Ben Keller is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Keller, Ben, Rangharajan Venkatesan, Steve Dai, et al.. (2023). A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm. IEEE Journal of Solid-State Circuits. 58(4). 1129–1141. 30 indexed citations
2.
Agnesina, Anthony, et al.. (2023). AutoDMP. 149–157. 26 indexed citations
3.
Keller, Ben, Rangharajan Venkatesan, Steve Dai, et al.. (2022). A 17–95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm. 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). 16–17. 27 indexed citations
4.
5.
Shao, Yakun Sophia, Rangharajan Venkatesan, Brian Zimmer, et al.. (2021). Simba. Communications of the ACM. 64(6). 107–116. 11 indexed citations
6.
Schmidt, Colin, Alon Amid, John Wright, et al.. (2020). Programmable Fine-Grained Power Management and System Analysis of RISC-V Vector Processors in 28-nm FD-SOI. IEEE Solid-State Circuits Letters. 3. 210–213. 2 indexed citations
7.
Zhang, Yanqing, Haoxing Ren, Ben Keller, & Brucek Khailany. (2020). Problem C. 1–4. 5 indexed citations
8.
Zimmer, Brian, Rangharajan Venkatesan, Yakun Sophia Shao, et al.. (2020). A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. IEEE Journal of Solid-State Circuits. 55(4). 920–932. 82 indexed citations
9.
Venkatesan, Rangharajan, Yakun Sophia Shao, Brian Zimmer, et al.. (2019). A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. 1–24. 10 indexed citations
10.
Zimmer, Brian, Rangharajan Venkatesan, Yakun Sophia Shao, et al.. (2019). A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. C300–C301. 40 indexed citations
11.
Venkatesan, Rangharajan, Yakun Sophia Shao, Jason Clemons, et al.. (2019). MAGNet: A Modular Accelerator Generator for Neural Networks. 1–8. 84 indexed citations
12.
Shao, Yakun Sophia, Jason Clemons, Rangharajan Venkatesan, et al.. (2019). Simba. 14–27. 248 indexed citations
13.
Keller, Ben, Sylvain Clerc, Fady Abouzeid, et al.. (2018). A 225 μm ${}^{2}$ Probe Single-Point Calibration Digital Temperature Sensor Using Body-Bias Adjustment in 28 nm FD-SOI CMOS. IEEE Solid-State Circuits Letters. 1(1). 14–17. 32 indexed citations
14.
Puggelli, Alberto, Ben Keller, Brian Zimmer, et al.. (2016). On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC. 125–128. 2 indexed citations
15.
Zimmer, Brian, Yunsup Lee, Alberto Puggelli, et al.. (2016). A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI. IEEE Journal of Solid-State Circuits. 51(4). 930–942. 51 indexed citations
16.
Lee, Yunsup, Andrew Waterman, Henry Cook, et al.. (2016). An Agile Approach to Building RISC-V Microprocessors. IEEE Micro. 36(2). 8–20. 70 indexed citations
17.
Blagojević, Milovan, et al.. (2016). A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI. 1–2. 35 indexed citations
18.
Zimmer, Brian, Yunsup Lee, Alberto Puggelli, et al.. (2015). A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. C316–C317. 25 indexed citations
19.
Lee, Yunsup, Brian Zimmer, Andrew Waterman, et al.. (2015). Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. 1–45. 9 indexed citations
20.
Keller, Ben, Matthew Fojtik, & Brucek Khailany. (2015). A Pausible Bisynchronous FIFO for GALS Systems. 1–8. 18 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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