Ruzica Jevtić

544 total citations
25 papers, 361 citations indexed

About

Ruzica Jevtić is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, Ruzica Jevtić has authored 25 papers receiving a total of 361 indexed citations (citations by other indexed papers that have themselves been cited), including 20 papers in Electrical and Electronic Engineering, 14 papers in Hardware and Architecture and 9 papers in Biomedical Engineering. Recurrent topics in Ruzica Jevtić's work include Low-power high-performance VLSI design (15 papers), Analog and Mixed-Signal Circuit Design (8 papers) and VLSI and FPGA Design Techniques (6 papers). Ruzica Jevtić is often cited by papers focused on Low-power high-performance VLSI design (15 papers), Analog and Mixed-Signal Circuit Design (8 papers) and VLSI and FPGA Design Techniques (6 papers). Ruzica Jevtić collaborates with scholars based in Spain, United States and France. Ruzica Jevtić's co-authors include Carlos Carreras, Borivoje Nikolić, Elad Alon, Krste Asanović, Milovan Blagojević, Hanh‐Phuc Le, Brian Zimmer, Ben Keller, Rimas Avižienis and Andrew Waterman and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Industrial Informatics and IEEE Electron Device Letters.

In The Last Decade

Ruzica Jevtić

23 papers receiving 347 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Ruzica Jevtić Spain	12	245	193	63	62	42	25	361
Witold A. Pleskacz Poland	11	317 1.3×	229 1.2×	90 1.4×	59 1.0×	29 0.7×	102	425
Mostafa E. Salehi Iran	10	209 0.9×	149 0.8×	23 0.4×	138 2.2×	57 1.4×	57	355
Shih-Hsu Huang Taiwan	13	472 1.9×	305 1.6×	40 0.6×	99 1.6×	83 2.0×	134	610
Ray Bittner United States	9	72 0.3×	146 0.8×	55 0.9×	161 2.6×	37 0.9×	14	306
Milovan Blagojević France	10	237 1.0×	143 0.7×	51 0.8×	83 1.3×	24 0.6×	12	320
René van Leuken Netherlands	10	185 0.8×	103 0.5×	14 0.2×	95 1.5×	29 0.7×	58	299
Giovanni Ansaloni Switzerland	15	365 1.5×	359 1.9×	128 2.0×	197 3.2×	55 1.3×	74	689
John M. Emmert United States	13	445 1.8×	415 2.2×	30 0.5×	71 1.1×	50 1.2×	39	542
Ing-Chao Lin Taiwan	12	432 1.8×	222 1.2×	101 1.6×	99 1.6×	41 1.0×	49	537
Xiaoyang Zeng China	11	300 1.2×	67 0.3×	97 1.5×	41 0.7×	41 1.0×	71	394

Countries citing papers authored by Ruzica Jevtić

Since Specialization

Citations

This map shows the geographic impact of Ruzica Jevtić's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Ruzica Jevtić with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Ruzica Jevtić more than expected).

Fields of papers citing papers by Ruzica Jevtić

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Ruzica Jevtić. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Ruzica Jevtić. The network helps show where Ruzica Jevtić may publish in the future.

Co-authorship network of co-authors of Ruzica Jevtić

This figure shows the co-authorship network connecting the top 25 collaborators of Ruzica Jevtić. A scholar is included among the top collaborators of Ruzica Jevtić based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Ruzica Jevtić. Ruzica Jevtić is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Jevtić, Ruzica, et al.. (2025). The effect of ECG data variability on side-channel attack success rate in wearable devices. Integration. 103. 102385–102385.

Jevtić, Ruzica, et al.. (2022). Methodology for Complete Decorrelation of Power Supply EM Side-Channel Signal and Sensitive Data. IEEE Transactions on Circuits & Systems II Express Briefs. 69(4). 2256–2260. 4 indexed citations

Caffarena, Gabriel, et al.. (2022). Hardware emulation of ECG sensors for biomedical embedded system design and teaching. 2022 IEEE 2nd Mysore Sub Section International Conference (MysuruCon). 1–6.

Jevtić, Ruzica, et al.. (2022). Side-channel Attack Countermeasure Based on Power Supply Modulation. 2022 30th European Signal Processing Conference (EUSIPCO). 618–622. 2 indexed citations

Jevtić, Ruzica, et al.. (2021). EM Side-Channel Countermeasure for Switched-Capacitor DC–DC Converters Based on Amplitude Modulation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29(6). 1061–1072. 10 indexed citations

Jevtić, Ruzica, et al.. (2018). Reconfigurable Switched Capacitor DC-DC Converter for Improved Security in IoT Devices. 4. 243–247. 5 indexed citations

Lee, Yunsup, Andrew Waterman, Henry Cook, et al.. (2016). An Agile Approach to Building RISC-V Microprocessors. IEEE Micro. 36(2). 8–20. 70 indexed citations

Zimmer, Brian, Yunsup Lee, Alberto Puggelli, et al.. (2016). A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI. IEEE Journal of Solid-State Circuits. 51(4). 930–942. 51 indexed citations

Hiienkari, Markus, et al.. (2015). Fully integrated DC-DC converter and a 0.4V 32-bit CPU with timing-error prevention supplied from a prototype 1.55V Li-ion battery. 48. C320–C321. 15 indexed citations

10.

Zimmer, Brian, Yunsup Lee, Alberto Puggelli, et al.. (2015). A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. C316–C317. 25 indexed citations

11.

Cardes, Fernando, et al.. (2015). A MEMS microphone interface based on a CMOS LC oscillator and a digital sigma-delta modulator. 2233–2236. 2 indexed citations

12.

Carreras, Carlos, et al.. (2014). Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes. Journal of Systems Architecture. 60(7). 579–591. 4 indexed citations

13.

Jevtić, Ruzica, et al.. (2013). Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits. IEEE Transactions on Industrial Informatics. 10(1). 393–398. 12 indexed citations

14.

Jeon, Jaeseok, Louis Hutin, Ruzica Jevtić, et al.. (2012). Multiple-Input Relay Design for More Compact Implementation of Digital Logic Circuits. IEEE Electron Device Letters. 33(2). 281–283. 12 indexed citations

15.

Jevtić, Ruzica, et al.. (2011). Power estimation of dividers implemented in FPGAs. 313–318. 4 indexed citations

16.

Jevtić, Ruzica & Carlos Carreras. (2011). A complete dynamic power estimation model for data-paths in FPGA DSP designs. Integration. 45(2). 172–185. 11 indexed citations

17.

Jevtić, Ruzica & Carlos Carreras. (2010). Power Measurement Methodology for FPGA Devices. IEEE Transactions on Instrumentation and Measurement. 60(1). 237–247. 19 indexed citations

18.

Jevtić, Ruzica & Carlos Carreras. (2009). Power Estimation of Embedded Multiplier Blocks in FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18(5). 835–839. 27 indexed citations

19.

Jevtić, Ruzica, et al.. (2009). Floorplan-based FPGA interconnect power estimation in DSP circuits. 53–60. 2 indexed citations

20.

Jevtić, Ruzica, Carlos Carreras, & Gabriel Caffarena. (2008). Fast and accurate power estimation of FPGA DSP components based on high-level switching activity models. International Journal of Electronics. 95(7). 653–668. 8 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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