Yu‐Liang Wu
- Electrical and Electronic Engineering top 10%
- Hardware and Architecture top 2%
- Mechanical Engineering top 10%
- Computer Networks and Communications top 10%
- Biomedical Engineering
- Co-authors
- Malgorzata Marek-SadowskaMingjia SunKuo LiuXingguo XiongC. K. WongGilbert H. YoungWenqi HuangDong Xiang
- Topics
- VLSI and FPGA Design Techniques (48 papers)VLSI and Analog Circuit Testing (41 papers)Interconnection Networks and Systems (25 papers)
- Cited by
- Hardware and ArchitectureComputer Graphics and Computer-Aided DesignIndustrial and Manufacturing Engineering
- Partner nations
- Hong KongChinaUnited States
In The Last Decade
Yu‐Liang Wu
100 papers receiving 830 citations
Peers
Comparison fields: 5 of 92
- Electrical and Electronic Engineering 450
- Hardware and Architecture 302
- Mechanical Engineering 195
- Computer Networks and Communications 152
- Biomedical Engineering 112
Countries citing papers authored by Yu‐Liang Wu
This map shows the geographic impact of Yu‐Liang Wu's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Yu‐Liang Wu with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Yu‐Liang Wu more than expected).
Fields of papers citing papers by Yu‐Liang Wu
This network shows the impact of papers produced by Yu‐Liang Wu. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Yu‐Liang Wu. The network helps show where Yu‐Liang Wu may publish in the future.
Co-authorship network of co-authors of Yu‐Liang Wu
This figure shows the co-authorship network connecting the top 25 collaborators of Yu‐Liang Wu. A scholar is included among the top collaborators of Yu‐Liang Wu based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Yu‐Liang Wu. Yu‐Liang Wu is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 0 | |
| 2 | 0 | |
| 3 | 0 | |
| 4 | 1 | |
| 5 | 3 | |
| 6 | 5 | |
| 7 | 1 | |
| 8 | 4 | |
| 9 | 3 | |
| 10 | 6 | |
| 11 | 1 | |
| 12 | 3 | |
| 13 | 9 | |
| 14 | 1 | |
| 15 | Interconnection Graph Problem. | 1 |
| 16 | An Efficient exact router for hyper-universal switching bok | 1 |
| 17 | 19 | |
| 18 | 15 | |
| 19 | 2 | |
| 20 | 17 |
About Yu‐Liang Wu
Yu‐Liang Wu is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Graphics and Computer-Aided Design, having authored 114 papers that have together received 874 indexed citations. Recurring topics across this work include VLSI and FPGA Design Techniques (48 papers), VLSI and Analog Circuit Testing (41 papers) and Interconnection Networks and Systems (25 papers). The work is most often cited by research in Hardware and Architecture (302 citations), Computer Graphics and Computer-Aided Design (42 citations) and Industrial and Manufacturing Engineering (97 citations). Yu‐Liang Wu has collaborated with scholars based in Hong Kong, China and United States. Frequent co-authors include Malgorzata Marek-Sadowska, Mingjia Sun, Kuo Liu, Xingguo Xiong, C. K. Wong, Gilbert H. Young, Wenqi Huang, Dong Xiang, W.B. Jone and Jiaguang Sun. Their work appears in journals such as Free Radical Biology and Medicine, European Journal of Operational Research and IEEE Access.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.