Alain Greiner

3.0k total citations · 1 hit paper
43 papers, 1.3k citations indexed

About

Alain Greiner is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Networks and Communications. According to data from OpenAlex, Alain Greiner has authored 43 papers receiving a total of 1.3k indexed citations (citations by other indexed papers that have themselves been cited), including 35 papers in Hardware and Architecture, 24 papers in Electrical and Electronic Engineering and 19 papers in Computer Networks and Communications. Recurrent topics in Alain Greiner's work include Embedded Systems Design Techniques (20 papers), Parallel Computing and Optimization Techniques (19 papers) and VLSI and Analog Circuit Testing (16 papers). Alain Greiner is often cited by papers focused on Embedded Systems Design Techniques (20 papers), Parallel Computing and Optimization Techniques (19 papers) and VLSI and Analog Circuit Testing (16 papers). Alain Greiner collaborates with scholars based in France, United States and Switzerland. Alain Greiner's co-authors include Pièrre Guerrier, Cesar Albenes Zeferino, Frédéric Pétrot, Ivan Miro-Panades, François Pêcheux, M. Combes, Jan G. Korvink, Rolando Marbot, Mohamed Dessouky and Andreas Kaiser and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and Computers & Electrical Engineering.

In The Last Decade

Alain Greiner

37 papers receiving 1.2k citations

Hit Papers

A generic architecture for on-chip packet-switched interc... 2000 2026 2008 2017 2000 100 200 300 400 500
What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

  1. A generic architecture for on-chip packet-switched interconnections
    2000 572 citations Alain Greiner et al. profile →

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Alain Greiner France 13 1.2k 1.0k 563 206 36 43 1.3k
Greg Ruhl United States 11 876 0.8× 771 0.8× 670 1.2× 93 0.5× 33 0.9× 11 1.2k
D.N. Jayasimha United States 12 755 0.7× 440 0.4× 490 0.9× 137 0.7× 39 1.1× 33 945
R. Saleh Canada 16 1.3k 1.1× 1.2k 1.2× 991 1.8× 258 1.3× 46 1.3× 44 1.7k
Sriram Vangal United States 5 731 0.6× 655 0.7× 472 0.8× 96 0.5× 17 0.5× 6 944
Martti Forsell Finland 10 1.1k 1.0× 920 0.9× 420 0.7× 177 0.9× 10 0.3× 63 1.2k
Evgeny Bolotin United States 20 1.2k 1.0× 1.1k 1.1× 480 0.9× 138 0.7× 10 0.3× 26 1.4k
José Flich Spain 25 1.8k 1.6× 1.2k 1.2× 980 1.7× 254 1.2× 29 0.8× 148 1.9k
Mikael Millberg Sweden 12 1.6k 1.4× 1.2k 1.2× 756 1.3× 322 1.6× 10 0.3× 22 1.7k
Tiju Jacob United States 7 928 0.8× 799 0.8× 684 1.2× 129 0.6× 28 0.8× 8 1.2k
Xinping Zhu United States 6 845 0.7× 728 0.7× 431 0.8× 154 0.7× 4 0.1× 11 963

Countries citing papers authored by Alain Greiner

Since Specialization
Citations

This map shows the geographic impact of Alain Greiner's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Alain Greiner with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Alain Greiner more than expected).

Fields of papers citing papers by Alain Greiner

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Alain Greiner. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Alain Greiner. The network helps show where Alain Greiner may publish in the future.

Co-authorship network of co-authors of Alain Greiner

This figure shows the co-authorship network connecting the top 25 collaborators of Alain Greiner. A scholar is included among the top collaborators of Alain Greiner based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Alain Greiner. Alain Greiner is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Liu, Hao, et al.. (2015). RWT: Suppressing Write-Through Cost When Coherence is Not Needed. HAL (Le Centre pour la Communication Scientifique Directe). 7. 434–439. 2 indexed citations
2.
Schwarz, Christian, et al.. (2009). Multi-compartment: A new architecture for secure co-hosting on SoC. HAL (Le Centre pour la Communication Scientifique Directe). 124–127. 7 indexed citations
3.
Greiner, Alain, et al.. (2008). Multisynchronous and Fully Asynchronous NoCs for GALS Architectures. IEEE Design & Test of Computers. 25(6). 572–580. 39 indexed citations
4.
Atitallah, Rabie Ben, et al.. (2008). Estimating Energy Consumption for an MPSoC Architectural Exploration. 3 indexed citations
5.
Greiner, Alain, et al.. (2007). Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture. Design, Automation, and Test in Europe. 1090–1095. 24 indexed citations
6.
Greiner, Alain, et al.. (2007). Two efficient synchronous asynchronous converters well-suited for networks-on-chip in GALS architectures. Integration. 41(1). 17–26. 22 indexed citations
7.
Pétrot, Frédéric, et al.. (2006). On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures. SPIRE - Sciences Po Institutional REpository. 53–60. 28 indexed citations
8.
Greiner, Alain, et al.. (2004). STEPS: experimenting a new software-based strategy for testing SoCs containing P1500-compliant IP cores. Design, Automation, and Test in Europe. 1. 10712. 5 indexed citations
9.
Greiner, Alain, et al.. (2004). STEPS: experimenting a new software-based strategy for testing SoCs containing P1500-compliant IP cores. Proceedings Design, Automation and Test in Europe Conference and Exhibition. 712–713. 5 indexed citations
10.
Greiner, Alain, et al.. (2003). Micro-Network for SoC: Implementation of a 32-Port SPIN network. Design, Automation, and Test in Europe. 11128–11129. 37 indexed citations
11.
Greiner, Alain, et al.. (2002). On the design of mixed-mode simulators for modern VLSI circuits. 2. 1168–1171. 1 indexed citations
12.
Greiner, Alain, et al.. (2002). A high density datapath compiler mixing random logic with optimized blocks. 194–198. 4 indexed citations
13.
Greiner, Alain, et al.. (2002). A high performance modular embedded ROM architecture. 2. 1057–1060. 4 indexed citations
14.
Greiner, Alain, et al.. (2002). TAS: an accurate timing analyser for CMOS VLSI. 261–265. 6 indexed citations
15.
Dessouky, Mohamed, Andreas Kaiser, Marie‐Minerve Louërat, & Alain Greiner. (2001). Analog design for reuse - case study: very low-voltage sigma-delta modulator. Design, Automation, and Test in Europe. 353–360. 5 indexed citations
16.
Greiner, Alain, et al.. (1994). Multilevel logic optimization of very high complexity circuits. European Design Automation Conference. 14–19. 3 indexed citations
17.
Greiner, Alain & Frédéric Pétrot. (1994). Using C to write portable CMOS VLSI module generators. European Design Automation Conference. 676–681. 10 indexed citations
18.
Greiner, Alain, et al.. (1992). DESB, a functional abstractor for CMOS VLSI circuits. European Design Automation Conference. 22–27. 7 indexed citations
19.
Greiner, Alain, et al.. (1991). GENVIEW: a portable source-level debugger for macrocell generators. European Design Automation Conference. 408–412. 2 indexed citations
20.
Greiner, Alain, et al.. (1991). TAS: an accurate timing analyser for CMOS VLSI. European Design Automation Conference. 261–265. 7 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact

Breakdown of academic impact, for papers by Greg Ruhl Breakdown of academic impact, for papers by D.N. Jayasimha Breakdown of academic impact, for papers by R. Saleh Breakdown of academic impact, for papers by Sriram Vangal Breakdown of academic impact, for papers by Martti Forsell Breakdown of academic impact, for papers by Evgeny Bolotin Breakdown of academic impact, for papers by José Flich Breakdown of academic impact, for papers by Mikael Millberg Breakdown of academic impact, for papers by Tiju Jacob Breakdown of academic impact, for papers by Xinping Zhu
Rankless by CCL
2026