Vyacheslav Rovner

537 citations

16 papers · 399 indexed · h-index 9

Hardware and Architecture top 5%
- VLSI and Analog Circuit Testing 6
Electrical and Electronic Engineering top 10%
- Advancements in Photolithography Techniques 11
- VLSI and FPGA Design Techniques 10
- 3D IC and TSV technologies 6
- Low-power high-performance VLSI design 5
- Advancements in Semiconductor Devices and Circuit Design 3
- Semiconductor materials and devices 3
Industrial and Manufacturing Engineering top 10%
Computer Networks and Communications
Biomedical Engineering
- Advanced Surface Polishing Techniques 1

Co-authors: Andrzej J. Strojwas Larry Pileggi Lawrence T. Pileggi Lars W. Liebmann Herman Schmit Y. Takegawa P. Gopalakrishnan G. A. Northrop
Cited by: Hardware and Architecture Electrical and Electronic Engineering Industrial and Manufacturing Engineering
Journals: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1 paper)Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE (8 papers)
Partner nations: United States

In The Last Decade

Vyacheslav Rovner

16 papers receiving 365 citations

Peers

Countries citing papers authored by Vyacheslav Rovner

Since Specialization

Citations

This map shows the geographic impact of Vyacheslav Rovner's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Vyacheslav Rovner with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Vyacheslav Rovner more than expected).

Fields of papers citing papers by Vyacheslav Rovner

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Vyacheslav Rovner. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Vyacheslav Rovner. The network helps show where Vyacheslav Rovner may publish in the future.

Co-authorship network

The 12 scholars most cited alongside Vyacheslav Rovner, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Vyacheslav Rovner Line = papers co-authored together Vyacheslav Rovner links everyone, so they are left out of the graph.

All Works

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16 of 16 papers shown

#	Work
1	Performance and manufacturability trade-offs of pattern minimization for sub-22nm technology nodes Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE ·Vyacheslav Rovner,Tejas Jhaveri,Daniel Morris,Andrzej J. Strojwas,Larry Pileggi	2011	2
2	Application of the cost-per-good-die metric for process design co-optimization Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE ·Tejas Jhaveri,Ümüt Arslan,Vyacheslav Rovner,Andrzej J. Strojwas,Larry Pileggi	2010	1
3	Enabling application-specific integrated circuits on limited pattern constructs Daniel Morris,Vyacheslav Rovner,Larry Pileggi,Andrzej J. Strojwas,Kaushik Vaidyanathan	2010	14
4	Demonstrating the benefits of template-based design-technology co-optimization Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE ·Lars W. Liebmann,Jason Hibbeler,Nathaniel Hieter,Larry Pileggi,Tejas Jhaveri,Matthew Moe,Vyacheslav Rovner	2010	1
5	Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Tejas Jhaveri,Vyacheslav Rovner,Lars W. Liebmann,Larry Pileggi,Andrzej J. Strojwas,Jason Hibbeler	2010	69
6	Economic assessment of lithography strategies for the 22nm technology node Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE ·Tejas Jhaveri,Andrzej J. Strojwas,Larry Pileggi,Vyacheslav Rovner	2009	5
7	Creating an affordable 22nm node using design-lithography co-optimization Andrzej J. Strojwas,Tejas Jhaveri,Vyacheslav Rovner,Larry Pileggi	2009	3
8	Simplify to survive: prescriptive layouts ensure profitable scaling to 32nm and beyond Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE ·Lars W. Liebmann,Larry Pileggi,Jason Hibbeler,Vyacheslav Rovner,Tejas Jhaveri,G. A. Northrop	2009	37
9	OPC simplification and mask cost reduction using regular design fabrics Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE ·Tejas Jhaveri,Ian Stobert,Lars W. Liebmann,Paul Karakatsanis,Vyacheslav Rovner,Andrzej J. Strojwas,Larry Pileggi	2009	12
10	Enabling technology scaling with "in production" lithography processes Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE ·Tejas Jhaveri,Andrzej J. Strojwas,Larry Pileggi,Vyacheslav Rovner	2008	7
11	Maximization of layout printability/manufacturability by extreme layout regularity Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE ·Tejas Jhaveri,Larry Pileggi,Vyacheslav Rovner,Andrzej J. Strojwas	2006	33
12	Design Methodology of Regular Logic Bricks for Robust Integrated Circuits Kim Yaw Tong,Vyacheslav Rovner,Lawrence T. Pileggi,V. Kheterpal	2006	8
13	Design methodology for IC manufacturability based on regular logic-bricks V. Kheterpal,Vyacheslav Rovner,Thiago Hersan,D. Motiani,Y. Takegawa,Andrzej J. Strojwas,Lawrence T. Pileggi	2005	26
14	Design methodology for IC manufacturability based on regular logic-bricks V. Kheterpal,Vyacheslav Rovner,Thiago Hersan,D. Motiani,Y. Takegawa,Andrzej J. Strojwas,Lawrence T. Pileggi	2005	70
15	Regular logic fabrics for a via patterned gate array (VPGA) K. Y. Tong,V. Kheterpal,Vyacheslav Rovner,Lawrence T. Pileggi,Herman Schmit	2004	27
16	Exploring regular fabrics to optimize the performance-cost trade-off Larry Pileggi,Herman Schmit,Andrzej J. Strojwas,P. Gopalakrishnan,V. Kheterpal,A. Koorapaty,Chetan Patel,Vyacheslav Rovner,K. Y. Tong	2003	84

About Vyacheslav Rovner

Vyacheslav Rovner is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Industrial and Manufacturing Engineering, having authored 16 papers that have together received 399 indexed citations. Recurring topics across this work include Advancements in Photolithography Techniques (11 papers), VLSI and FPGA Design Techniques (10 papers), VLSI and Analog Circuit Testing (6 papers), 3D IC and TSV technologies (6 papers), Low-power high-performance VLSI design (5 papers), Advancements in Semiconductor Devices and Circuit Design (3 papers), Semiconductor materials and devices (3 papers) and Advanced Surface Polishing Techniques (1 paper). The work is most often cited by research in Hardware and Architecture (191 citations), Electrical and Electronic Engineering (376 citations) and Industrial and Manufacturing Engineering (36 citations). Vyacheslav Rovner has collaborated with scholars based in United States. Frequent co-authors include Andrzej J. Strojwas, Larry Pileggi, Lawrence T. Pileggi, Lars W. Liebmann, Herman Schmit, Y. Takegawa, P. Gopalakrishnan, G. A. Northrop, Daniel Morris and Kaushik Vaidyanathan. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE.

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