K. Kushida

718 total citations
29 papers, 572 citations indexed

About

K. Kushida is a scholar working on Electrical and Electronic Engineering, Atomic and Molecular Physics, and Optics and Biomedical Engineering. According to data from OpenAlex, K. Kushida has authored 29 papers receiving a total of 572 indexed citations (citations by other indexed papers that have themselves been cited), including 28 papers in Electrical and Electronic Engineering, 6 papers in Atomic and Molecular Physics, and Optics and 6 papers in Biomedical Engineering. Recurrent topics in K. Kushida's work include Low-power high-performance VLSI design (21 papers), Advancements in Semiconductor Devices and Circuit Design (15 papers) and Semiconductor materials and devices (15 papers). K. Kushida is often cited by papers focused on Low-power high-performance VLSI design (21 papers), Advancements in Semiconductor Devices and Circuit Design (15 papers) and Semiconductor materials and devices (15 papers). K. Kushida collaborates with scholars based in Japan. K. Kushida's co-authors include Atsushi Kawasumi, Y. Takeyama, Osamu Hirabayashi, Tomoaki Yabe, Hiroyuki Hara, Kazutaka Ikegami, Shinobu Fujita, Keiko Abe, Hiroki Noguchi and Junichi Ito and has published in prestigious journals such as IEEE Journal of Solid-State Circuits and IEICE Technical Report; IEICE Tech. Rep..

In The Last Decade

K. Kushida

28 papers receiving 549 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
K. Kushida Japan 13 532 134 114 78 52 29 572
Atsushi Kawasumi Japan 13 590 1.1× 163 1.2× 114 1.0× 93 1.2× 65 1.3× 44 644
Mohit Gupta Belgium 14 559 1.1× 85 0.6× 121 1.1× 39 0.5× 54 1.0× 45 645
Jung Pill Kim United States 16 520 1.0× 85 0.6× 259 2.3× 67 0.9× 38 0.7× 27 563
Hideto Hidaka Japan 14 549 1.0× 275 2.1× 43 0.4× 166 2.1× 66 1.3× 54 662
W. Reohr United States 10 350 0.7× 169 1.3× 146 1.3× 129 1.7× 44 0.8× 18 444
L. C. Tran United States 7 310 0.6× 53 0.4× 173 1.5× 56 0.7× 18 0.3× 13 368
Yuanqing Cheng China 13 523 1.0× 141 1.1× 190 1.7× 143 1.8× 26 0.5× 62 626
Ki Chul Chun United States 11 526 1.0× 121 0.9× 209 1.8× 98 1.3× 38 0.7× 18 640
Richard Dorrance United States 10 404 0.8× 82 0.6× 183 1.6× 97 1.2× 40 0.8× 25 515
Takashi Ohsawa Japan 17 713 1.3× 89 0.7× 203 1.8× 76 1.0× 57 1.1× 73 778

Countries citing papers authored by K. Kushida

Since Specialization
Citations

This map shows the geographic impact of K. Kushida's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by K. Kushida with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites K. Kushida more than expected).

Fields of papers citing papers by K. Kushida

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by K. Kushida. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by K. Kushida. The network helps show where K. Kushida may publish in the future.

Co-authorship network of co-authors of K. Kushida

This figure shows the co-authorship network connecting the top 25 collaborators of K. Kushida. A scholar is included among the top collaborators of K. Kushida based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with K. Kushida. K. Kushida is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Noguchi, Hiroki, Kazutaka Ikegami, Satoshi Takaya, et al.. (2016). 7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. 132–133. 55 indexed citations
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Ikegami, Kazutaka, Hiroshi Noguchi, M. Amano, et al.. (2014). Low power and high density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques. 28.1.1–28.1.4. 21 indexed citations
4.
Ikegami, Kazutaka, Hiroshi Noguchi, M. Amano, et al.. (2014). A 4ns, 0.9V write voltage embedded perpendicular STT-MRAM fabricated by MTJ-Last process. 109. 1–2. 5 indexed citations
5.
Hirabayashi, Osamu, et al.. (2013). A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit. IEEE Journal of Solid-State Circuits. 49(1). 118–126. 15 indexed citations
6.
Noguchi, Hiroki, K. Kushida, Kazutaka Ikegami, et al.. (2013). A 250-MHz 256b-I/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors. 2013. 108–109. 44 indexed citations
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Kawasumi, Atsushi, et al.. (2011). A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers. IEEE Journal of Solid-State Circuits. 46(11). 2545–2551. 33 indexed citations
10.
Hirabayashi, Osamu, et al.. (2010). A Configurable SRAM with Constant-Negative-Level Write Buffer for Low Voltage Operation with 0.149μm2 Cell in 32nm High-k Metal Gate CMOS. IEICE Technical Report; IEICE Tech. Rep.. 110(9). 1–6. 2 indexed citations
11.
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Hirabayashi, Osamu, et al.. (2009). A Process-Variation-Tolerant Dual-Power-Supply SRAM with 0.179μm2 Cell in 40nm CMOS Using Level-Programmable Wordline Driver. IEICE Technical Report; IEICE Tech. Rep.. 109(2). 21–26. 7 indexed citations
13.
Hirabayashi, Osamu, Atsushi Kawasumi, Akira Suzuki, et al.. (2009). A process-variation-tolerant dual-power-supply SRAM with 0.179&#x00B5;m<sup>2</sup> Cell in 40nm CMOS using level-programmable wordline driver. 458–459,459a. 73 indexed citations
14.
Kawasumi, Atsushi, et al.. (2009). A low supply voltage operation SRAM with HCI trimmed sense amplifiers. 221–224. 4 indexed citations
15.
Kawasumi, Atsushi, et al.. (2008). A Single-Power-Supply 0.7V 1GHz 45nm SRAM with an Asymmetrical Unit β-ratio Memory Cell. IEICE Technical Report; IEICE Tech. Rep.. 108(6). 1–6. 1 indexed citations
16.
Kawasumi, Atsushi, Tomoaki Yabe, Y. Takeyama, et al.. (2008). A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-ß-ratio Memory Cell. 382–622. 29 indexed citations
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Takeyama, Y., et al.. (2006). A Low Leakage SRAM Macro With Replica Cell Biasing Scheme. IEEE Journal of Solid-State Circuits. 41(4). 815–822. 28 indexed citations
20.
Hirabayashi, Osamu, Akira Suzuki, Tomoaki Yabe, et al.. (2003). DFT techniques for wafer-level at-speed testing of high-speed SRAMs. 164–169. 3 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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