K. Kushida

718 citations

29 papers · 572 indexed · h-index 13

Co-authors: Atsushi Kawasumi Y. Takeyama Osamu Hirabayashi Tomoaki Yabe Hiroyuki Hara Kazutaka Ikegami Shinobu Fujita Keiko Abe
Topics: Low-power high-performance VLSI design (21 papers)Advancements in Semiconductor Devices and Circuit Design (15 papers)Semiconductor materials and devices (15 papers)
Cited by: Hardware and Architecture Electrical and Electronic Engineering Atomic and Molecular Physics, and Optics
Journals: IEEE Journal of Solid-State CircuitsIEICE Technical Report; IEICE Tech. Rep.
Partner nations: Japan

In The Last Decade

K. Kushida

28 papers receiving 549 citations

Peers

Countries citing papers authored by K. Kushida

Since Specialization

Citations

This map shows the geographic impact of K. Kushida's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by K. Kushida with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites K. Kushida more than expected).

Fields of papers citing papers by K. Kushida

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by K. Kushida. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by K. Kushida. The network helps show where K. Kushida may publish in the future.

Co-authorship network of co-authors of K. Kushida

This figure shows the co-authorship network connecting the top 25 collaborators of K. Kushida. A scholar is included among the top collaborators of K. Kushida based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with K. Kushida. K. Kushida is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme 2016 ·Hiroki Noguchi,Kazutaka Ikegami,Satoshi Takaya,(unknown),K. Kushida,Atsushi Kawasumi,Hiroyuki Hara,Keiko Abe,Naoharu Shimomura,Junichi Ito,Shinobu Fujita,(unknown),Hiroshi Nakamura	55
2	MTJ-based "normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and last level cache based on 1T-1MTJ cell and novel error handling scheme 2015 ·Kazutaka Ikegami,Hiroshi Noguchi,Satoshi Takaya,(unknown),M. Amano,Keiko Abe,K. Kushida,E. Kitagawa,(unknown),N. Shimomura,(unknown),Atsushi Kawasumi,Hiroyuki Hara,Junichi Ito,Shinobu Fujita	8
3	Low power and high density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques 2014 ·Kazutaka Ikegami,Hiroshi Noguchi,(unknown),M. Amano,Keiko Abe,K. Kushida,E. Kitagawa,(unknown),N. Shimomura,(unknown),(unknown),(unknown),Atsushi Kawasumi,Hiroyuki Hara,Junichi Ito,Shinobu Fujita	21
4	A 4ns, 0.9V write voltage embedded perpendicular STT-MRAM fabricated by MTJ-Last process 2014 ·Kazutaka Ikegami,Hiroshi Noguchi,(unknown),M. Amano,Keiko Abe,K. Kushida,E. Kitagawa,(unknown),N. Shimomura,Atsushi Kawasumi,Hiroyuki Hara,Junichi Ito,Shinobu Fujita	5
5	A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit 2013 ·IEEE Journal of Solid-State Circuits ·(unknown),Osamu Hirabayashi,Y. Takeyama,(unknown),Atsushi Kawasumi,K. Kushida,(unknown),(unknown),(unknown),Tomoaki Yabe,(unknown)	15
6	A 250-MHz 256b-I/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors 2013 ·Hiroki Noguchi,K. Kushida,Kazutaka Ikegami,Keiko Abe,E. Kitagawa,(unknown),(unknown),Atsushi Kawasumi,Hiroyuki Hara,Shinobu Fujita	44
7	A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs 2012 ·Atsushi Kawasumi,Y. Takeyama,Osamu Hirabayashi,K. Kushida,(unknown),(unknown),(unknown),Tomoaki Yabe	6
8	A trimless, 0.5V–1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access 2011 ·K. Kushida,Osamu Hirabayashi,(unknown),Hiroyuki Hara,Atsushi Kawasumi,Akira Suzuki,Y. Takeyama,Y. Fujimura,(unknown),(unknown),Shinya Sasaki,Tomoaki Yabe	2
9	A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers 2011 ·IEEE Journal of Solid-State Circuits ·(unknown),Atsushi Kawasumi,(unknown),Y. Takeyama,Osamu Hirabayashi,K. Kushida,(unknown),(unknown),Tomoaki Yabe	33
10	A Configurable SRAM with Constant-Negative-Level Write Buffer for Low Voltage Operation with 0.149μm2 Cell in 32nm High-k Metal Gate CMOS 2010 ·IEICE Technical Report; IEICE Tech. Rep. ·(unknown),Osamu Hirabayashi,(unknown),(unknown),Atsushi Kawasumi,Y. Takeyama,K. Kushida,(unknown),(unknown),(unknown),Tomoaki Yabe	2
11	A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm<sup>2</sup> cell in 32nm high-<inf>k</inf> metal-gate CMOS 2010 ·(unknown),Osamu Hirabayashi,(unknown),(unknown),Atsushi Kawasumi,Y. Takeyama,K. Kushida,(unknown),(unknown),(unknown),Tomoaki Yabe	35
12	A Process-Variation-Tolerant Dual-Power-Supply SRAM with 0.179μm2 Cell in 40nm CMOS Using Level-Programmable Wordline Driver 2009 ·IEICE Technical Report; IEICE Tech. Rep. ·(unknown),Osamu Hirabayashi,Atsushi Kawasumi,(unknown),Y. Takeyama,K. Kushida,(unknown),(unknown),(unknown),(unknown),(unknown),(unknown),Tomoaki Yabe	7
13	A process-variation-tolerant dual-power-supply SRAM with 0.179µm<sup>2</sup> Cell in 40nm CMOS using level-programmable wordline driver 2009 ·Osamu Hirabayashi,Atsushi Kawasumi,Akira Suzuki,Y. Takeyama,K. Kushida,Tadahiro Sasaki,(unknown),(unknown),Y. Fujimura,Tomoharu Nakazato,(unknown),(unknown),Tomoaki Yabe	73
14	A low supply voltage operation SRAM with HCI trimmed sense amplifiers 2009 ·Atsushi Kawasumi,Y. Takeyama,Osamu Hirabayashi,K. Kushida,(unknown),Tomoaki Yabe	4
15	A Single-Power-Supply 0.7V 1GHz 45nm SRAM with an Asymmetrical Unit β-ratio Memory Cell 2008 ·IEICE Technical Report; IEICE Tech. Rep. ·(unknown),Atsushi Kawasumi,Tomoaki Yabe,Y. Takeyama,Osamu Hirabayashi,K. Kushida,(unknown),(unknown),(unknown),(unknown),(unknown)	1
16	A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-ß-ratio Memory Cell 2008 ·Atsushi Kawasumi,Tomoaki Yabe,Y. Takeyama,Osamu Hirabayashi,K. Kushida,(unknown),T. Sasaki,(unknown),(unknown),Y. Fujimura,(unknown)	29
17	A 0.7V single-supply SRAM with 0.495um<sup>2</sup> cell in 65nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme 2008 ·K. Kushida,(unknown),(unknown),Atsushi Kawasumi,Osamu Hirabayashi,Y. Takeyama,(unknown),(unknown),(unknown),Tomoaki Yabe	12
18	Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation 2008 ·(unknown),Tomoaki Yabe,Osamu Hirabayashi,Y. Takeyama,K. Kushida,Tadahiro Sasaki,(unknown)	3
19	A Low Leakage SRAM Macro With Replica Cell Biasing Scheme 2006 ·IEEE Journal of Solid-State Circuits ·Y. Takeyama,Hiroyuki Otake,Osamu Hirabayashi,K. Kushida,(unknown)	28
20	DFT techniques for wafer-level at-speed testing of high-speed SRAMs 2003 ·Osamu Hirabayashi,Akira Suzuki,Tomoaki Yabe,Atsushi Kawasumi,Y. Takeyama,K. Kushida,(unknown),(unknown)	3

About K. Kushida

K. Kushida is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Atomic and Molecular Physics, and Optics, having authored 29 papers that have together received 572 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (21 papers), Advancements in Semiconductor Devices and Circuit Design (15 papers) and Semiconductor materials and devices (15 papers). The work is most often cited by research in Hardware and Architecture (134 citations), Electrical and Electronic Engineering (532 citations) and Atomic and Molecular Physics, and Optics (114 citations). K. Kushida has collaborated with scholars based in Japan. Frequent co-authors include Atsushi Kawasumi, Y. Takeyama, Osamu Hirabayashi, Tomoaki Yabe, Hiroyuki Hara, Kazutaka Ikegami, Shinobu Fujita, Keiko Abe, Hiroki Noguchi and Junichi Ito. Their work appears in journals such as IEEE Journal of Solid-State Circuits and IEICE Technical Report; IEICE Tech. Rep..

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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