Tapas Dutta

1.1k total citations
45 papers, 871 citations indexed

About

Tapas Dutta is a scholar working on Electrical and Electronic Engineering, Materials Chemistry and Biomedical Engineering. According to data from OpenAlex, Tapas Dutta has authored 45 papers receiving a total of 871 indexed citations (citations by other indexed papers that have themselves been cited), including 44 papers in Electrical and Electronic Engineering, 13 papers in Materials Chemistry and 10 papers in Biomedical Engineering. Recurrent topics in Tapas Dutta's work include Semiconductor materials and devices (39 papers), Advancements in Semiconductor Devices and Circuit Design (30 papers) and Ferroelectric and Negative Capacitance Devices (17 papers). Tapas Dutta is often cited by papers focused on Semiconductor materials and devices (39 papers), Advancements in Semiconductor Devices and Circuit Design (30 papers) and Ferroelectric and Negative Capacitance Devices (17 papers). Tapas Dutta collaborates with scholars based in United Kingdom, India and United States. Tapas Dutta's co-authors include Yogesh Singh Chauhan, Girish Pahwa, Sourabh Khandelwal, Sayeef Salahuddin, Chenming Hu, Vihar Georgiev, Asen Asenov, Saurabh Sinha, Amit Ranjan Trivedi and S. Bala Kumar and has published in prestigious journals such as SHILAP Revista de lepidopterología, IEEE Transactions on Electron Devices and Nanotechnology.

In The Last Decade

Tapas Dutta

40 papers receiving 848 citations

Peers

Tapas Dutta
Jin Cai United States
A. Walke Belgium
Ankit Jain United States
J. Johnson United States
Navid Paydavosi United States
M. Togo Japan
Jin Cai United States
Tapas Dutta
Citations per year, relative to Tapas Dutta Tapas Dutta (= 1×) peers Jin Cai

Countries citing papers authored by Tapas Dutta

Since Specialization
Citations

This map shows the geographic impact of Tapas Dutta's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Tapas Dutta with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Tapas Dutta more than expected).

Fields of papers citing papers by Tapas Dutta

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Tapas Dutta. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Tapas Dutta. The network helps show where Tapas Dutta may publish in the future.

Co-authorship network of co-authors of Tapas Dutta

This figure shows the co-authorship network connecting the top 25 collaborators of Tapas Dutta. A scholar is included among the top collaborators of Tapas Dutta based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Tapas Dutta. Tapas Dutta is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
2.
Dutta, Tapas, et al.. (2025). Interplay of Short-Channel and Narrow-Width Effects in FDSOI Transistors at Cryogenic Temperatures. IEEE Transactions on Electron Devices. 72(7). 3407–3414. 3 indexed citations
3.
Dixit, Ankit, et al.. (2025). Mobility and intrinsic performance of silicon-based nanosheet FETs at 3 nm CMOS and beyond. Solid-State Electronics. 229. 109172–109172.
4.
Sengupta, Amretashis, et al.. (2024). Analysis of Random Discrete Dopants Embedded Nanowire Resonant Tunnelling Diodes for Generation of Physically Unclonable Functions. IEEE Transactions on Nanotechnology. 23. 815–821. 3 indexed citations
5.
Dixit, Ankit, et al.. (2024). Unravelling the Impact of Random Dopant Fluctuations on Si-Based 3nm NSFET: A NEGF Analysis. ENLIGHTEN (Jurnal Bimbingan dan Konseling Islam). 5–8. 1 indexed citations
6.
Dutta, Tapas, et al.. (2023). Convolutional Machine Learning Method for Accelerating Nonequilibrium Green’s Function Simulations in Nanosheet Transistor. IEEE Transactions on Electron Devices. 70(10). 5448–5453. 8 indexed citations
7.
Dutta, Tapas, et al.. (2023). Fully Convolutional Generative Machine Learning Method for Accelerating Non-Equilibrium Green’s Function Simulations. ENLIGHTEN (Jurnal Bimbingan dan Konseling Islam). 169–172. 1 indexed citations
8.
Sengupta, Amretashis, et al.. (2022). Statistical device simulations of III-V nanowire resonant tunneling diodes as physical unclonable functions source. Solid-State Electronics. 194. 108339–108339. 2 indexed citations
9.
Medina-Bailón, Cristina, Tapas Dutta, Daniel Nagy, et al.. (2021). Simulation and Modeling of Novel Electronic Device Architectures with NESS (Nano-Electronic Simulation Software): A Modular Nano TCAD Simulation Framework. Micromachines. 12(6). 680–680. 11 indexed citations
10.
Medina-Bailón, Cristina, Tapas Dutta, Fikru Adamu-Lema, et al.. (2020). Nano-Electronic Simulation Software (NESS): A Novel Open-Source TCAD Simulation Environment. SHILAP Revista de lepidopterología. 3(4). 1–8. 6 indexed citations
11.
Pahwa, Girish, et al.. (2018). Physical Insights on Negative Capacitance Transistors in Nonhysteresis and Hysteresis Regimes: MFMIS Versus MFIS Structures. IEEE Transactions on Electron Devices. 65(3). 867–873. 110 indexed citations
12.
Dutta, Tapas, Hamilton Carrillo-Nuñez, Meng Duan, et al.. (2018). NESS: new flexible Nano-Electronic Simulation Software. ENLIGHTEN (Jurnal Bimbingan dan Konseling Islam). 22–25. 17 indexed citations
13.
Pahwa, Girish, et al.. (2017). Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure. IEEE Transactions on Electron Devices. 64(3). 1366–1374. 88 indexed citations
14.
Dutta, Tapas, et al.. (2017). Performance Evaluation of 7-nm Node Negative Capacitance FinFET-Based SRAM. IEEE Electron Device Letters. 38(8). 1161–1164. 75 indexed citations
15.
Dutta, Tapas, et al.. (2017). Impact of Process Variations on Negative Capacitance FinFET Devices and Circuits. IEEE Electron Device Letters. 39(1). 147–150. 48 indexed citations
16.
Pahwa, Girish, Tapas Dutta, Sourabh Khandelwal, et al.. (2016). Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part II: Model Validation. IEEE Transactions on Electron Devices. 63(12). 4986–4992. 145 indexed citations
17.
Pahwa, Girish, Tapas Dutta, Sourabh Khandelwal, et al.. (2016). Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model Description. IEEE Transactions on Electron Devices. 63(12). 4981–4985. 123 indexed citations
19.
Dutta, Tapas, et al.. (2016). Impact of Channel Thickness Variation on Bandstructure and Source-to-Drain Tunneling in Ultra-Thin Body III-V MOSFETs. IEEE Journal of the Electron Devices Society. 4(2). 66–71. 35 indexed citations
20.
Dutta, Tapas & Sudeb Dasgupta. (2009). Scaling issues in nanoscale double gate FinFETs with source/drain underlap. 1–4. 2 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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