Jouke Verbree

469 total citations
8 papers, 357 citations indexed

About

Jouke Verbree is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Automotive Engineering. According to data from OpenAlex, Jouke Verbree has authored 8 papers receiving a total of 357 indexed citations (citations by other indexed papers that have themselves been cited), including 8 papers in Electrical and Electronic Engineering, 5 papers in Hardware and Architecture and 1 paper in Automotive Engineering. Recurrent topics in Jouke Verbree's work include 3D IC and TSV technologies (7 papers), VLSI and Analog Circuit Testing (5 papers) and Advancements in Photolithography Techniques (4 papers). Jouke Verbree is often cited by papers focused on 3D IC and TSV technologies (7 papers), VLSI and Analog Circuit Testing (5 papers) and Advancements in Photolithography Techniques (4 papers). Jouke Verbree collaborates with scholars based in Netherlands, Belgium and United States. Jouke Verbree's co-authors include Erik Jan Marinissen, Mario Konijnenburg, Brandon Noia, Krishnendu Chakrabarty, Dimitrios Velenis, Philippe Roussel, S.K. Goel, Sandeep Goel, Said Hamdioui and Mottaqiallah Taouil and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and Journal of Electronic Testing.

In The Last Decade

Jouke Verbree

8 papers receiving 344 citations

Peers

Countries citing papers authored by Jouke Verbree

Since Specialization

Citations

This map shows the geographic impact of Jouke Verbree's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Jouke Verbree with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Jouke Verbree more than expected).

Fields of papers citing papers by Jouke Verbree

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Jouke Verbree. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Jouke Verbree. The network helps show where Jouke Verbree may publish in the future.

Co-authorship network of co-authors of Jouke Verbree

This figure shows the co-authorship network connecting the top 25 collaborators of Jouke Verbree. A scholar is included among the top collaborators of Jouke Verbree based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Jouke Verbree. Jouke Verbree is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

8 of 8 papers shown

#	Work	Indexed citations
1	Junction Optimization for Embedded 40nm FN/FN Flash Memory 2015 ·(unknown), (unknown), (unknown), B. Schippers, (unknown), (unknown), (unknown), Yu Chen, (unknown), (unknown), K. van Dijk, Jouke Verbree, (unknown), (unknown), (unknown), (unknown)	2
2	Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs 2011 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Brandon Noia, Krishnendu Chakrabarty, S.K. Goel, Erik Jan Marinissen, Jouke Verbree	43
3	A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper 2011 ·Journal of Electronic Testing ·Erik Jan Marinissen, (unknown), Mario Konijnenburg, Jouke Verbree	33
4	On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs 2010 ·Mottaqiallah Taouil, Said Hamdioui, Jouke Verbree, Erik Jan Marinissen	29
5	3D DfT architecture for pre-bond and post-bond testing 2010 ·Erik Jan Marinissen, (unknown), Jouke Verbree, Mario Konijnenburg	52
6	A structured and scalable test access architecture for TSV-based 3D stacked ICs 2010 ·Erik Jan Marinissen, Jouke Verbree, Mario Konijnenburg	119
7	On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking 2010 ·Jouke Verbree, Erik Jan Marinissen, Philippe Roussel, Dimitrios Velenis	40
8	Test-architecture optimization for TSV-based 3D stacked ICs 2010 ·Brandon Noia, Sandeep Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree	39

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact