N. Nalla Anandakumar

523 total citations
14 papers, 254 citations indexed

About

N. Nalla Anandakumar is a scholar working on Hardware and Architecture, Artificial Intelligence and Electrical and Electronic Engineering. According to data from OpenAlex, N. Nalla Anandakumar has authored 14 papers receiving a total of 254 indexed citations (citations by other indexed papers that have themselves been cited), including 13 papers in Hardware and Architecture, 7 papers in Artificial Intelligence and 7 papers in Electrical and Electronic Engineering. Recurrent topics in N. Nalla Anandakumar's work include Physical Unclonable Functions (PUFs) and Hardware Security (13 papers), Cryptographic Implementations and Security (7 papers) and Integrated Circuits and Semiconductor Failure Analysis (6 papers). N. Nalla Anandakumar is often cited by papers focused on Physical Unclonable Functions (PUFs) and Hardware Security (13 papers), Cryptographic Implementations and Security (7 papers) and Integrated Circuits and Semiconductor Failure Analysis (6 papers). N. Nalla Anandakumar collaborates with scholars based in Kazakhstan, India and United States. N. Nalla Anandakumar's co-authors include Mohammad Hashmi, Somitra Kumar Sanadhya, Mark Tehranipoor, Muhammad Akmal Chaudhary, Kimia Zamiri Azar, Mark Tehranipoor, Farimah Farahmandi and Fahim Rahman and has published in prestigious journals such as IEEE Access, IEEE Transactions on Circuits & Systems II Express Briefs and ACM Journal on Emerging Technologies in Computing Systems.

In The Last Decade

N. Nalla Anandakumar

14 papers receiving 243 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
N. Nalla Anandakumar Kazakhstan	8	188	140	85	65	49	14	254
Nathalie Bochard France	7	180 1.0×	149 1.1×	144 1.7×	95 1.5×	52 1.1×	19	299
Hyunho Kang Japan	9	117 0.6×	99 0.7×	72 0.8×	49 0.8×	56 1.1×	33	221
Dai Yamamoto Japan	9	217 1.2×	198 1.4×	28 0.3×	55 0.8×	108 2.2×	15	249
Liang Yao China	10	143 0.8×	123 0.9×	143 1.7×	65 1.0×	12 0.2×	39	266
Sachin Taneja Singapore	9	211 1.1×	199 1.4×	40 0.5×	64 1.0×	57 1.2×	26	314
Fatemeh Tehranipoor United States	11	148 0.8×	117 0.8×	47 0.6×	75 1.2×	37 0.8×	30	244
Aijiao Cui China	11	435 2.3×	344 2.5×	60 0.7×	101 1.6×	75 1.5×	47	485
Davide Bellizia Italy	14	309 1.6×	174 1.2×	151 1.8×	229 3.5×	20 0.4×	34	435
Helena Handschuh France	11	145 0.8×	95 0.7×	93 1.1×	168 2.6×	37 0.8×	24	296
Sayandeep Saha India	10	167 0.9×	113 0.8×	37 0.4×	145 2.2×	41 0.8×	31	257

Countries citing papers authored by N. Nalla Anandakumar

Since Specialization

Citations

This map shows the geographic impact of N. Nalla Anandakumar's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by N. Nalla Anandakumar with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites N. Nalla Anandakumar more than expected).

Fields of papers citing papers by N. Nalla Anandakumar

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by N. Nalla Anandakumar. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by N. Nalla Anandakumar. The network helps show where N. Nalla Anandakumar may publish in the future.

Co-authorship network of co-authors of N. Nalla Anandakumar

This figure shows the co-authorship network connecting the top 25 collaborators of N. Nalla Anandakumar. A scholar is included among the top collaborators of N. Nalla Anandakumar based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with N. Nalla Anandakumar. N. Nalla Anandakumar is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

14 of 14 papers shown

Tehranipoor, Mark, N. Nalla Anandakumar, & Farimah Farahmandi. (2023). Hardware Security Training, Hands-on!. 2 indexed citations

Anandakumar, N. Nalla, et al.. (2023). PSC-Watermark: Power Side Channel Based IP Watermarking Using Clock Gates. 1–6. 4 indexed citations

Anandakumar, N. Nalla, Mohammad Hashmi, & Somitra Kumar Sanadhya. (2022). Field Programmable Gate Array based elliptic curve Menezes‐Qu‐Vanstone key agreement protocol realization using Physical Unclonable Function and true random number generator primitives. IET Circuits Devices & Systems. 16(5). 382–398. 9 indexed citations

Anandakumar, N. Nalla, Mohammad Hashmi, & Muhammad Akmal Chaudhary. (2022). Implementation of Efficient XOR Arbiter PUF on FPGA With Enhanced Uniqueness and Security. IEEE Access. 10. 129832–129842. 21 indexed citations

Anandakumar, N. Nalla, Mohammad Hashmi, & Somitra Kumar Sanadhya. (2022). Design and Analysis of FPGA-based PUFs with Enhanced Performance for Hardware-oriented Security. ACM Journal on Emerging Technologies in Computing Systems. 18(4). 1–26. 15 indexed citations

Anandakumar, N. Nalla, et al.. (2021). FPGA Implementations of Espresso Stream Cipher. 1–6. 1 indexed citations

Anandakumar, N. Nalla, Mohammad Hashmi, & Mark Tehranipoor. (2021). FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures. Integration. 81. 175–194. 43 indexed citations

Anandakumar, N. Nalla, Somitra Kumar Sanadhya, & Mohammad Hashmi. (2020). Design, Implementation and Analysis of Efficient Hardware-Based Security Primitives. 198–199. 5 indexed citations

Anandakumar, N. Nalla, Mohammad Hashmi, & Somitra Kumar Sanadhya. (2020). Efficient and Lightweight FPGA-based Hybrid PUFs with Improved Performance. Microprocessors and Microsystems. 77. 103180–103180. 16 indexed citations

10.

Anandakumar, N. Nalla, et al.. (2020). Design and Analysis of Hardware Trojan Threats in Reconfigurable Hardware. 2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE). 1–5. 1 indexed citations

11.

Anandakumar, N. Nalla, Somitra Kumar Sanadhya, & Mohammad Hashmi. (2019). FPGA-Based True Random Number Generation Using Programmable Delays in Oscillator-Rings. IEEE Transactions on Circuits & Systems II Express Briefs. 67(3). 570–574. 87 indexed citations

12.

Anandakumar, N. Nalla, et al.. (2018). Reconfigurable Hardware Architecture for Authenticated Key Agreement Protocol Over Binary Edwards Curve. ACM Transactions on Reconfigurable Technology and Systems. 11(2). 1–19. 11 indexed citations

13.

Anandakumar, N. Nalla, Mohammad Hashmi, & Somitra Kumar Sanadhya. (2017). Compact Implementations of FPGA-based PUFs with Enhanced Performance. 161–166. 35 indexed citations

14.

Anandakumar, N. Nalla, et al.. (2012). Correlation power analysis attack of AES on FPGA using customized communication protocol. 683–688. 4 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact