S. Y. Hou

726 total citations
20 papers, 395 citations indexed

About

S. Y. Hou is a scholar working on Electrical and Electronic Engineering, Electronic, Optical and Magnetic Materials and Biomedical Engineering. According to data from OpenAlex, S. Y. Hou has authored 20 papers receiving a total of 395 indexed citations (citations by other indexed papers that have themselves been cited), including 16 papers in Electrical and Electronic Engineering, 4 papers in Electronic, Optical and Magnetic Materials and 3 papers in Biomedical Engineering. Recurrent topics in S. Y. Hou's work include 3D IC and TSV technologies (14 papers), Electronic Packaging and Soldering Technologies (8 papers) and Copper Interconnects and Reliability (4 papers). S. Y. Hou is often cited by papers focused on 3D IC and TSV technologies (14 papers), Electronic Packaging and Soldering Technologies (8 papers) and Copper Interconnects and Reliability (4 papers). S. Y. Hou collaborates with scholars based in Taiwan, China and United States. S. Y. Hou's co-authors include K. C. Ting, Douglas Yu, C. T. Wang, W.C. Chiou, Cheng‐Hsien Wu, Christine Chiu, Shin-Puu Jeng, Chin‐Wei Lu, Chung-Hao Tsai and Yuchen Hu and has published in prestigious journals such as International Journal of Hydrogen Energy, IEEE Transactions on Wireless Communications and IEEE Transactions on Electron Devices.

In The Last Decade

S. Y. Hou

16 papers receiving 376 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
S. Y. Hou Taiwan 11 343 55 52 41 35 20 395
C. T. Wang Taiwan 10 338 1.0× 48 0.9× 62 1.2× 37 0.9× 32 0.9× 13 379
K. C. Ting Taiwan 8 267 0.8× 52 0.9× 43 0.8× 22 0.5× 33 0.9× 10 317
W.C. Chiou Taiwan 11 467 1.4× 60 1.1× 75 1.4× 49 1.2× 37 1.1× 22 517
A. Sharma United States 6 327 1.0× 25 0.5× 46 0.9× 29 0.7× 21 0.6× 8 362
Suresh Ramalingam United States 13 513 1.5× 60 1.1× 117 2.3× 50 1.2× 30 0.9× 38 563
Riko Radojcic United States 11 282 0.8× 38 0.7× 38 0.7× 13 0.3× 43 1.2× 45 312
Islam A. Salama United States 7 311 0.9× 61 1.1× 70 1.3× 25 0.6× 30 0.9× 24 409
Chong Ser Choong Singapore 10 340 1.0× 28 0.5× 64 1.2× 48 1.2× 7 0.2× 47 375
Yoichiro Kurita Japan 9 374 1.1× 18 0.3× 67 1.3× 37 0.9× 21 0.6× 32 387
M. J. Interrante United States 6 463 1.3× 27 0.5× 71 1.4× 52 1.3× 33 0.9× 7 487

Countries citing papers authored by S. Y. Hou

Since Specialization
Citations

This map shows the geographic impact of S. Y. Hou's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by S. Y. Hou with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites S. Y. Hou more than expected).

Fields of papers citing papers by S. Y. Hou

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by S. Y. Hou. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by S. Y. Hou. The network helps show where S. Y. Hou may publish in the future.

Co-authorship network of co-authors of S. Y. Hou

This figure shows the co-authorship network connecting the top 25 collaborators of S. Y. Hou. A scholar is included among the top collaborators of S. Y. Hou based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with S. Y. Hou. S. Y. Hou is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Hou, S. Y., et al.. (2025). EF-RT-DETR: a efficient focused real-time DETR model for pavement distress detection. Journal of Real-Time Image Processing. 22(2). 6 indexed citations
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Huang, Yueting, et al.. (2024). Cu-based heterojunction catalysts for electrocatalytic nitrate reduction to ammonia. Journal of Fuel Chemistry and Technology. 52(12). 1857–1864.
5.
Hou, S. Y., et al.. (2024). Caprock Safety Evaluation Method in CCUS Based on Latin Hypercube Sampling: A case study of a block reservoir. Journal of Physics Conference Series. 2834(1). 12165–12165.
6.
Hou, S. Y., et al.. (2024). Reconfigurable Intelligent Surface Aided Hybrid Beamforming: Optimal Placement and Beamforming Design. IEEE Transactions on Wireless Communications. 23(9). 12003–12019. 11 indexed citations
7.
Hou, S. Y., et al.. (2023). Supercarrier Redistribution Layers to Realize Ultra Large 2.5D Wafer Scale Packaging by CoWoS. 510–514. 13 indexed citations
8.
Hu, Yuchen, et al.. (2023). CoWoS Architecture Evolution for Next Generation HPC on 2.5D System in Package. 1022–1026. 34 indexed citations
9.
Lu, Chin‐Wei, Christine Chiu, K. C. Ting, et al.. (2021). Wafer Level System Integration of the Fifth Generation CoWoS®-S with High Performance Si Interposer at 2500 mm2. 101–104. 55 indexed citations
10.
Tsai, Chung-Hsien, et al.. (2020). Design and Analysis of Logic-HBM2E Power Delivery System on CoWoS® Platform with Deep Trench Capacitor. 380–385. 18 indexed citations
11.
Hou, S. Y., Chung-Hsien Tsai, K. C. Ting, et al.. (2019). Integrated Deep Trench Capacitor in Si Interposer for CoWoS Heterogeneous Integration. 19.5.1–19.5.4. 35 indexed citations
12.
Ting, K. C., Tianjun Yu, C. T. Wang, et al.. (2017). Wafer level integration of an advanced logic-memory system through 2nd generation CoWoS® technology. T54–T55. 22 indexed citations
13.
Hou, S. Y., Christine Chiu, K. C. Ting, et al.. (2017). Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology. IEEE Transactions on Electron Devices. 64(10). 4071–4077. 139 indexed citations
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Fan, Cuncai, Catherine Chiu, Cheng-Yu Hsieh, et al.. (2014). A high-performance low-cost chip-on-Wafer package with sub-μm pitch Cu RDL. 1–2. 7 indexed citations
16.
Ibbotson, D. E., Arif Rahman, Kaushik Chanda, et al.. (2013). Manufacturability optimization and design validation studies for FPGA-based, 3D integrated circuits. Symposium on VLSI Technology. 3 indexed citations
17.
Kuo, Feng-Wei, Tzu-Jin Yeh, S. Y. Hou, et al.. (2013). High-performance inductors for integrated fan-out wafer level packaging (InFO-WLP). 6 indexed citations
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19.
Chiu, Catherine, Ta‐Chuan Yeh, S. Y. Hou, et al.. (2011). Electromigration study of micro bumps at Si/Si interface in 3DIC package for 28nm technology and beyond. 346–350. 15 indexed citations
20.
Hou, S. Y., Cho-Chiang Shih, C.H. Hsieh, et al.. (2010). Lead-free flip chip solution for 40 nm extreme low-k interconnect system. 9. 1–3. 2 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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