Ching-Te Chuang

1.7k citations

101 papers · 1.3k indexed · h-index 20

Impact in

Hardware and Architecture top 5%
- VLSI and Analog Circuit Testing
Electrical and Electronic Engineering top 5%
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Low-power high-performance VLSI design
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Advanced Memory and Neural Computing
- VLSI and FPGA Design Techniques

Papers in

Electrical and Electronic Engineering 101
- Advancements in Semiconductor Devices and Circuit Design 86
- Semiconductor materials and devices 74
- Low-power high-performance VLSI design 53
- Ferroelectric and Negative Capacitance Devices 17
- Integrated Circuits and Semiconductor Failure Analysis 14
- Electrostatic Discharge in Electronics 5
Hardware and Architecture 10
- VLSI and Analog Circuit Testing 8

Co-authors: Keunwoo Kim Pin Su Ming-Long Fan Vita Pi‐Ho Hu Jae‐Joon Kim Rahul Rao Rajiv Joshi Saibal Mukhopadhyay
Journals: IEEE Transactions on Electron Devices (15 papers)IEEE Electron Device Letters (5 papers)IEEE Transactions on Very Large Scale Integration (VLSI) Systems (4 papers)IEEE Journal of Solid-State Circuits (3 papers)Solid-State Electronics (2 papers)
Partner nations: Taiwan United States United Kingdom

In The Last Decade

Ching-Te Chuang

99 papers receiving 1.2k citations

Peers

Countries citing papers authored by Ching-Te Chuang

Since Specialization

Citations

This map shows the geographic impact of Ching-Te Chuang's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Ching-Te Chuang with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Ching-Te Chuang more than expected).

Fields of papers citing papers by Ching-Te Chuang

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Ching-Te Chuang. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Ching-Te Chuang. The network helps show where Ching-Te Chuang may publish in the future.

Co-authors

The 25 scholars most cited alongside Ching-Te Chuang, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Ching-Te Chuang Line = papers co-authored together Ching-Te Chuang links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	Impacts of work function variation and line-edge roughness on TFET and FinFET devices and logic circuits Terwelp, Franck Kayser, Ming-Long Fan, Vita Pi‐Ho Hu, Pin Su, Ching-Te Chuang	2014	6
2	Band-to-Band-Tunneling Leakage Suppression for Ultra-Thin-Body GeOI MOSFETs Using Transistor Stacking IEEE Electron Device Letters ·Vita Pi‐Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang	2012	11
3	Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·F Moussion, Rahul Rao, Jae‐Joon Kim, Ching-Te Chuang, Richard B. Brown	2012	9
4	Energy Efficient Bootstrapped CMOS Large RC-Load Driver Circuit for Ultra Low-Voltage VLSI Journal of Low Power Electronics and Applications ·H Narimatsu, Ching-Te Chuang	2012	4
5	8T single-ended sub-threshold SRAM with cross-point data-aware write operation Darrell B. Johnson, Maria Luiza de Medeiros Amaro, Ming-Hsien Tu, Shyh‐Jye Jou, Ching-Te Chuang	2011	6
6	Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·배현자, Ming-Long Fan, Vita Pi‐Ho Hu, Pin Su, Ching-Te Chuang	2011	34
7	Leakage-delay analysis of Ultra-Thin-Body GeOI devices and logic circuits Vita Pi‐Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang	2011	6
8	Threshold Voltage Design of UTB SOI SRAM With Improved Stability/Variability for Ultralow Voltage Near Subthreshold Operation IEEE Transactions on Nanotechnology ·Vita Pi‐Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang	2011	5
9	Investigation of stability and AC performance of sub-threshold FinFET SRAM Ming-Long Fan, Yusheng Wu, Vita Pi‐Ho Hu, Pin Su, Ching-Te Chuang	2010	2
10	Impacts of Contact Resistance and NBTI/PBTI on SRAM with High-? Metal-Gate Devices David Briggs, Ching-Te Chuang, Wei Hwang	2009	3
11	Optimal Dual-$V_{T}$ Design in Sub-100-nm PD/SOI and Double-Gate Technologies IEEE Transactions on Electron Devices ·Aditya Bansal, Jae‐Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy	2008	1
12	An On-Chip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process IEEE Journal of Solid-State Circuits ·Saibal Mukhopadhyay, Keunwoo Kim, K.A. Jenkins, Ching-Te Chuang, Kaushik Roy	2008	11
13	Independent-Gate Controlled Asymmetrical SRAM Cells in Double-Gate MOSFET Technology for Improved READ Stability Jae‐Joon Kim, Keunwoo Kim, Ching-Te Chuang	2006	5
14	Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy	2005	9
15	Design and CAD Challenges in sub-90nm CMOS Technologies International Conference on Computer Aided Design ·Kerry Bernstein, Ching-Te Chuang, Rajiv Joshi, Ruchir Puri	2003	55
16	Strained-Si devices and circuits for low-power applications Keunwoo Kim, Shanqing Lin, Ching-Te Chuang	2003	2
17	Strained-si devices and circuits for low-power applications Keunwoo Kim, Rajiv Joshi, Ching-Te Chuang	2003	3
18	New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology Sakhi Soanl, Bunga Chintia Utami, Ching-Te Chuang, Ebru Yesin, Maria de Fátima Bessa Soares	2003	0
19	Physical compact model for threshold voltage in short-channel double-gate devices Keunwoo Kim, J.G. Fossum, Ching-Te Chuang	2003	14
20	Design considerations of high-performance narrow-emitter bipolar transistors IEEE Electron Device Letters ·D.D. Tang, Tze-Chiang Chen, Ching-Te Chuang, G.P. Li, J.M.C. Stork, M. B. Ketchen, Darina Lurina, T.H. Ning	1987	25

About Ching-Te Chuang

Ching-Te Chuang is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Bioengineering, Biomedical Engineering and Cellular and Molecular Neuroscience, having authored 101 papers that have together received 1.3k indexed citations. Recurring topics across this work include Advancements in Semiconductor Devices and Circuit Design (86 papers), Semiconductor materials and devices (74 papers), Low-power high-performance VLSI design (53 papers), Ferroelectric and Negative Capacitance Devices (17 papers), Integrated Circuits and Semiconductor Failure Analysis (14 papers), VLSI and Analog Circuit Testing (8 papers), Analog and Mixed-Signal Circuit Design (6 papers) and Electrostatic Discharge in Electronics (5 papers). The work is most often cited by research in Hardware and Architecture (188 citations), Electrical and Electronic Engineering (1.2k citations), Biomedical Engineering (173 citations), Computer Networks and Communications (39 citations) and Structural Biology (2 citations). Ching-Te Chuang has collaborated with scholars based in Taiwan, United States and United Kingdom. Frequent co-authors include Keunwoo Kim, Pin Su, Ming-Long Fan, Vita Pi‐Ho Hu, Jae‐Joon Kim, Rahul Rao, Rajiv Joshi, Saibal Mukhopadhyay, C.J. Anderson and Ruchir Puri. Their work appears in journals such as IEEE Transactions on Electron Devices, IEEE Electron Device Letters, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Journal of Solid-State Circuits and Solid-State Electronics.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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