G. Goto

543 citations

32 papers · 405 indexed · h-index 10

Impact in

Hardware and Architecture top 5%
- VLSI and Analog Circuit Testing
- Parallel Computing and Optimization Techniques
Electrical and Electronic Engineering top 10%
- Low-power high-performance VLSI design
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- VLSI and FPGA Design Techniques

Papers in

Hardware and Architecture 8
- VLSI and Analog Circuit Testing 5
Electrical and Electronic Engineering 28
- Advancements in Semiconductor Devices and Circuit Design 11
- Low-power high-performance VLSI design 8
- Semiconductor materials and devices 8
- Integrated Circuits and Semiconductor Failure Analysis 6

Co-authors: Toshiro Sato H. Takanashi S. Yanagisawa Osamu Wada Akihisa Inoue Takeshi Go Tsuru T. Nakamura Koichi Yamashita
Journals: IEEE Journal of Solid-State Circuits (5 papers)IEEE Transactions on Electron Devices (5 papers)Japanese Journal of Applied Physics (1 paper)IEICE Transactions on Electronics (1 paper)IEEE Transactions on Very Large Scale Integration (VLSI) Systems (1 paper)
Partner nations: Japan

In The Last Decade

G. Goto

25 papers receiving 362 citations

Peers

Countries citing papers authored by G. Goto

Since Specialization

Citations

This map shows the geographic impact of G. Goto's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by G. Goto with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites G. Goto more than expected).

Fields of papers citing papers by G. Goto

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by G. Goto. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by G. Goto. The network helps show where G. Goto may publish in the future.

Co-authors

The 25 scholars most cited alongside G. Goto, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with G. Goto Line = papers co-authored together G. Goto links everyone, so they are left out of the graph.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

#	Work
1	A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor Max Hermann Poech, Hikaru Tamura, Kiyoshi Katō, Sustamy R. (Raffiky) Pinandia, Nadia Dumara Ruiz Silveira, Maureen W Mbugua, Tatsuya Onuki, Samantha Hume, E. L., C. S. Souza, Yasutaka Suzuki, Marco Antonio Ruíz Nieves, Tomoaki Atsumi, Yutaka Shionoiri, G. Goto, Jun Koyama, Masahiro Fujita, Shunpei Yamazaki	2014	9
2	A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers 杨成军, Ryusuke Egawa, Fernando Manuel Ponce Garcia, Hiroaki Kobayashi, G. Goto	2012	5
3	Complex Multiplier Suited for FPGA Structure Hafez Alsumairy, Azzeddine El Osrouti, Basavarajappa Sokke Rameshappa, G. Goto	2009	8
4	Gain Based Delay Balancing in the Deep Submicron Era ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ·Ryusuke Egawa, Azzeddine El Osrouti, Hiroaki Kobayashi, G. Goto	2008	1
5	Gain-based Delay Balancing Technique for Wave Pipelining ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ·杨成军, Ryusuke Egawa, Eckehart Stöve, G. Goto, Tadao Nakamura	2007	1
6	A Sophisticated Multiplier in Advanced CMOS Technologies ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ·Ryusuke Egawa, JING WANG, G. Goto, Tadao Nakamura	2006	0
7	A wafer-scale FFT processor featuring a repeatable building block Koichi Yamashita, Поденко А.В., Ruifeng Yuan, G. Goto	2003	1
8	A 64-bit floating-point processing unit with a horizontal instruction code for parallel operations Hongqin Chen, Hari Ponnamma Rani, LorenD. Grossman, Toshiro Sato, A. G. U. N. Wijesinghe, G. Goto	2002	2
9	A VLSI Processor Architecture for a Back-Propagation Accelerator IEICE Transactions on Electronics ·Yoshio Hirose, Elliot J. Kaback, Koichi Yamashita, G. Goto	1992	0
10	A Regularly Structured 54-bit Modified-Wallace-Tree Multiplier. IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·州博岡村, S Sharmila, Inventaire National Du Patrimoine Naturel, G. Goto	1991	4
11	A wafer-scale 170000-gate FFT processor with built-in test circuits IEEE Journal of Solid-State Circuits ·Koichi Yamashita, Поденко А.В., Ruifeng Yuan, G. Goto, J. Tyrwhitt Brooks, Michelle Lobo Andrade	1988	37
12	Modeling and analysis of transient latchup in double-well bulk CMOS IEEE Transactions on Electron Devices ·G. Goto, Hidenori Takahashi, Taro Nakamura	1986	7
13	A 240K transistor CMOS array with flexible allocation of memory and channels IEEE Journal of Solid-State Circuits ·Hari Ponnamma Rani, S. Sato, G. Goto, T. Nakamura, Hiroaki Kikuchi, Michelle Lobo Andrade	1985	12
14	Latch-up immunity against noise pulses in a CMOS double well structure G. Goto, Hari Ponnamma Rani, T. Nakamura	1983	16
15	Gunn-effect logic device using transverse extension of a high field domain IEEE Transactions on Electron Devices ·G. Goto, T. Nakamura, S. Hasuo, Zhilin Liu, أحمد عبد الحميد مصطفي	1976	4
16	Influence of carrier diffusion on an anode trapped domain formation in a transferred electron device IEEE Transactions on Electron Devices ·S. Hasuo, T. Nakamura, G. Goto, Zhilin Liu, H. Bano, Hitoshi Suzuki, أحمد عبد الحميد مصطفي	1976	10
17	Picosecond Gunn-effect carry generator for binary adders T. Nakamura, S. Hasuo, G. Goto, Zhilin Liu, أحمد عبد الحميد مصطفي	1975	4
18	Two-dimensional domain dynamics in a planar Schottky-gate Gunn-effect device IEEE Transactions on Electron Devices ·G. Goto, T. Nakamura, أحمد عبد الحميد مصطفي	1975	8
19	Control of Two-Dimensional High Field Domain in Gunn Effect Functional Devices Mee-Rae Koo, S. Hasuo, G. Goto, Zhilin Liu, H. Bano, Hajime Suzuki, أحمد عبد الحميد مصطفي	1974	2
20	Application of Gunn effect to subnanosecond full adder and full subtractor Proceedings of the IEEE ·أحمد عبد الحميد مصطفي, T. Nakamura, G. Goto	1973	4

About G. Goto

G. Goto is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Atomic and Molecular Physics, and Optics, Computational Theory and Mathematics and Biomedical Engineering, having authored 32 papers that have together received 405 indexed citations. Recurring topics across this work include Advancements in Semiconductor Devices and Circuit Design (11 papers), Low-power high-performance VLSI design (8 papers), Semiconductor materials and devices (8 papers), Semiconductor Quantum Structures and Devices (6 papers), Integrated Circuits and Semiconductor Failure Analysis (6 papers), Analog and Mixed-Signal Circuit Design (6 papers), VLSI and Analog Circuit Testing (5 papers) and Semiconductor materials and interfaces (3 papers). The work is most often cited by research in Hardware and Architecture (125 citations), Electrical and Electronic Engineering (365 citations), Computational Theory and Mathematics (72 citations), Signal Processing (36 citations) and Atomic and Molecular Physics, and Optics (68 citations). G. Goto has collaborated with scholars based in Japan. Frequent co-authors include Toshiro Sato, H. Takanashi, S. Yanagisawa, Osamu Wada, Akihisa Inoue, Takeshi Go Tsuru, T. Nakamura, T. Nakamura, Koichi Yamashita and S. Hasuo. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Electron Devices, Japanese Journal of Applied Physics, IEICE Transactions on Electronics and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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