S.H. Dhong

835 total citations
39 papers, 498 citations indexed

About

S.H. Dhong is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, S.H. Dhong has authored 39 papers receiving a total of 498 indexed citations (citations by other indexed papers that have themselves been cited), including 35 papers in Electrical and Electronic Engineering, 20 papers in Hardware and Architecture and 8 papers in Biomedical Engineering. Recurrent topics in S.H. Dhong's work include Low-power high-performance VLSI design (22 papers), Parallel Computing and Optimization Techniques (12 papers) and Advancements in Semiconductor Devices and Circuit Design (11 papers). S.H. Dhong is often cited by papers focused on Low-power high-performance VLSI design (22 papers), Parallel Computing and Optimization Techniques (12 papers) and Advancements in Semiconductor Devices and Circuit Design (11 papers). S.H. Dhong collaborates with scholars based in United States, Japan and Germany. S.H. Dhong's co-authors include Osamu Takahashi, Hwa-Joon Oh, J. A. Silberman, H. Peter Hofstee, Silvia Melitta Mueller, B. Flachs, T. Van Duzer, J. Leenstra, Christian Jacobi and Hiroaki Nishikawa and has published in prestigious journals such as Journal of Applied Physics, IEEE Journal of Solid-State Circuits and IEEE Transactions on Electron Devices.

In The Last Decade

S.H. Dhong

37 papers receiving 459 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
S.H. Dhong United States 13 351 267 117 85 65 39 498
G. Goto Japan 10 365 1.0× 125 0.5× 28 0.2× 72 0.8× 83 1.3× 32 405
Hongil Yoon South Korea 12 255 0.7× 104 0.4× 117 1.0× 23 0.3× 39 0.6× 49 366
Liming Xiu United States 12 403 1.1× 86 0.3× 61 0.5× 91 1.1× 212 3.3× 40 458
Ronald Scrofano United States 9 147 0.4× 236 0.9× 91 0.8× 98 1.2× 32 0.5× 17 320
M. Nagamatsu Japan 8 408 1.2× 148 0.6× 30 0.3× 62 0.7× 88 1.4× 18 459
Ki‐Young Choi South Korea 13 342 1.0× 506 1.9× 410 3.5× 39 0.5× 17 0.3× 34 726
S. Kulkarni United States 14 852 2.4× 209 0.8× 110 0.9× 67 0.8× 134 2.1× 33 957
Bruce Fleischer United States 10 170 0.5× 109 0.4× 41 0.4× 62 0.7× 35 0.5× 14 223
Kahng United States 6 309 0.9× 151 0.6× 36 0.3× 51 0.6× 53 0.8× 9 355
Yizheng Ye China 10 238 0.7× 122 0.5× 80 0.7× 22 0.3× 65 1.0× 68 322

Countries citing papers authored by S.H. Dhong

Since Specialization
Citations

This map shows the geographic impact of S.H. Dhong's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by S.H. Dhong with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites S.H. Dhong more than expected).

Fields of papers citing papers by S.H. Dhong

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by S.H. Dhong. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by S.H. Dhong. The network helps show where S.H. Dhong may publish in the future.

Co-authorship network of co-authors of S.H. Dhong

This figure shows the co-authorship network connecting the top 25 collaborators of S.H. Dhong. A scholar is included among the top collaborators of S.H. Dhong based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with S.H. Dhong. S.H. Dhong is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Dhong, S.H., et al.. (2014). A 4-GHz universal high-frequency on-chip testing platform for IP validation. 1–6. 4 indexed citations
2.
Riley, M., B. Flachs, S.H. Dhong, et al.. (2007). Implementation of the 65nm Cell Broadband Engine. 717–720. 2 indexed citations
3.
Oh, Hwa-Joon, et al.. (2006). A Fully Pipelined Single-Precision Floating-Point Unit in the Synergistic Processor Element of a CELL Processor. IEEE Journal of Solid-State Circuits. 41(4). 759–771. 46 indexed citations
4.
Takahashi, Osamu, S.H. Dhong, B. Flachs, et al.. (2005). The circuit design of the synergistic processor element of a CELL processor. International Conference on Computer Aided Design. 111–117. 2 indexed citations
5.
Flachs, B., S. Asano, S.H. Dhong, et al.. (2005). A streaming processing unit for a CELL processor. 134–135. 93 indexed citations
6.
Mueller, Silvia Melitta, et al.. (2005). The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor. 20. 59–67. 33 indexed citations
7.
Takahashi, Osamu, S.H. Dhong, B. Flachs, et al.. (2005). The circuits and physical design of the synergistic processor element of a CELL processor. 20–23. 13 indexed citations
8.
Silberman, J. A., et al.. (2005). Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor. IEEE Micro. 25(5). 30–38. 12 indexed citations
9.
Hofstee, H. Peter, N. Aoki, D. Boerstler, et al.. (2002). A 1 GHz single-issue 64 b PowerPC processor. 92–93. 27 indexed citations
10.
Takahashi, Osamu, S.H. Dhong, R.H. Dennard, et al.. (2002). 1 GHz fully pipelined 3.7 ns address access time 8 k×1024 embedded DRAM macro. 5. 396–397. 2 indexed citations
11.
Takahashi, Osamu, et al.. (2002). High-speed, power-conscious circuit design techniques for high-performance computing. 279–282. 2 indexed citations
12.
Allen, D.H., S.H. Dhong, H. Peter Hofstee, et al.. (2000). Custom circuit design as a driver of microprocessor performance. IBM Journal of Research and Development. 44(6). 799–822. 24 indexed citations
13.
Takahashi, Osamu, S.H. Dhong, R.H. Dennard, et al.. (2000). WP 24.3 1GHz Fully Pipelined 3.7ns Address Access Time 8kx1024 Embedded DRAM Macro. 3 indexed citations
14.
Takahashi, Osamu, S.H. Dhong, R.H. Dennard, et al.. (2000). 1-GHz fully pipelined 3.7-ns address access time 8 k/spl times/1024 embedded synchronous DRAM macro. IEEE Journal of Solid-State Circuits. 35(11). 1673–1679. 8 indexed citations
15.
Takahashi, Osamu, N. Aoki, J. A. Silberman, & S.H. Dhong. (1999). A 1-GHz logic circuit family with sense amplifiers. IEEE Journal of Solid-State Circuits. 34(5). 616–622. 4 indexed citations
16.
Scheuerlein, R.E., Y. Katayama, T. Kirihata, et al.. (1992). A Pulsed Sensing Scheme with a Limited Bit-Line Swing. IEICE Transactions on Electronics. 576–580. 2 indexed citations
17.
Franch, R., S.H. Dhong, & R.E. Scheuerlein. (1992). A large V/sub DS/ data retention test pattern for DRAM's. IEEE Journal of Solid-State Circuits. 27(8). 1214–1217. 5 indexed citations
18.
Lu, Nicky, G. Bronner, Koji Kitamura, et al.. (1989). A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing. IEEE Journal of Solid-State Circuits. 24(5). 1198–1205. 14 indexed citations
19.
Sun, J.Y.-C., et al.. (1986). Design and characteristics of a lightly doped drain (LDD) device fabricated with self-aligned titanium disilicide. IEEE Transactions on Electron Devices. 33(3). 345–353. 10 indexed citations
20.
Dhong, S.H. & T. Van Duzer. (1980). Minimum-width control-current pulse for Josephson logic gates. IEEE Transactions on Electron Devices. 27(10). 1965–1973. 12 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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