M. Kakumu
About
In The Last Decade
M. Kakumu
52 papers receiving 725 citations
Peers
Comparison fields: 5 of 36
- Electrical and Electronic Engineering 738
- Biomedical Engineering 134
- Hardware and Architecture 122
- Atomic and Molecular Physics, and Optics 43
- Computer Networks and Communications 37
Countries citing papers authored by M. Kakumu
This map shows the geographic impact of M. Kakumu's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by M. Kakumu with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites M. Kakumu more than expected).
Fields of papers citing papers by M. Kakumu
This network shows the impact of papers produced by M. Kakumu. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by M. Kakumu. The network helps show where M. Kakumu may publish in the future.
Co-authorship network of co-authors of M. Kakumu
This figure shows the co-authorship network connecting the top 25 collaborators of M. Kakumu. A scholar is included among the top collaborators of M. Kakumu based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with M. Kakumu. M. Kakumu is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 1 | |
| 2 | 1 | |
| 3 | 0 | |
| 4 | 27 | |
| 5 | 24 | |
| 6 | 2 | |
| 7 | 1 | |
| 8 | 4 | |
| 9 | Design Methodology of Deep Submicron CMOS Devices for 1 V Operation (Special Issue on Low-Power LSI Technologies) | 1 |
| 10 | 2 | |
| 11 | 1 | |
| 12 | Process and Device Technologies of CMOS Devices for Low-Voltage Operation (Special Section on Low-Power and Low-Voltage Integrated Circuits) | 2 |
| 13 | Submicron 3D Surface-Orientation-Optimized CMOS Technology | 7 |
| 14 | 1 | |
| 15 | 6 | |
| 16 | Deep Trench Well Isolation for 256Kb 6T CMOS Static RAM | 2 |
| 17 | Submicron MLDO NMOSFETs for 5V Operation | 14 |
| 18 | 12 | |
| 19 | 2 | |
| 20 | Work Function Controlled Silicide Technology for Submicron CMOS | 1 |
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.