T. Sudo

569 total citations
32 papers, 445 citations indexed

About

T. Sudo is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, T. Sudo has authored 32 papers receiving a total of 445 indexed citations (citations by other indexed papers that have themselves been cited), including 28 papers in Electrical and Electronic Engineering, 9 papers in Hardware and Architecture and 5 papers in Biomedical Engineering. Recurrent topics in T. Sudo's work include Advancements in Semiconductor Devices and Circuit Design (12 papers), VLSI and Analog Circuit Testing (7 papers) and VLSI and FPGA Design Techniques (6 papers). T. Sudo is often cited by papers focused on Advancements in Semiconductor Devices and Circuit Design (12 papers), VLSI and Analog Circuit Testing (7 papers) and VLSI and FPGA Design Techniques (6 papers). T. Sudo collaborates with scholars based in Japan and United States. T. Sudo's co-authors include A. Yoshii, T. Takada, S. Horiguchi, M. Tomizawa, M. Ida, Yokoyama, K. Yokoyama, T. Adachi, Toshiki Kondo and Masanao Aoki and has published in prestigious journals such as Proceedings of the IEEE, IEEE Journal of Solid-State Circuits and IEEE Transactions on Microwave Theory and Techniques.

In The Last Decade

T. Sudo

30 papers receiving 397 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
T. Sudo Japan	14	399	90	55	46	21	32	445
J.I. Raffel United States	12	209 0.5×	82 0.9×	50 0.9×	45 1.0×	33 1.6×	35	356
J.-H. Chern United States	8	374 0.9×	24 0.3×	102 1.9×	22 0.5×	23 1.1×	24	414
Jamil Kawa United States	13	406 1.0×	92 1.0×	99 1.8×	112 2.4×	32 1.5×	40	515
G. Goto Japan	10	365 0.9×	68 0.8×	125 2.3×	83 1.8×	28 1.3×	32	405
Donald O. Pederson United States	6	223 0.6×	34 0.4×	47 0.9×	58 1.3×	18 0.9×	11	267
A.M. Mohsen United States	15	613 1.5×	50 0.6×	187 3.4×	69 1.5×	59 2.8×	44	679
M. Kakumu Japan	13	738 1.8×	43 0.5×	122 2.2×	134 2.9×	37 1.8×	58	783
H.C. Poon Japan	10	657 1.6×	108 1.2×	25 0.5×	98 2.1×	18 0.9×	15	697
W. Kleinfelder United States	6	213 0.5×	113 1.3×	114 2.1×	17 0.4×	73 3.5×	8	336
L.J. Giacoletto United States	8	356 0.9×	106 1.2×	9 0.2×	45 1.0×	20 1.0×	35	431

Countries citing papers authored by T. Sudo

Since Specialization

Citations

This map shows the geographic impact of T. Sudo's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by T. Sudo with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites T. Sudo more than expected).

Fields of papers citing papers by T. Sudo

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by T. Sudo. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by T. Sudo. The network helps show where T. Sudo may publish in the future.

Co-authorship network of co-authors of T. Sudo

This figure shows the co-authorship network connecting the top 25 collaborators of T. Sudo. A scholar is included among the top collaborators of T. Sudo based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with T. Sudo. T. Sudo is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Akazawa, Y., et al.. (2003). Packaging technologies for 500-MHz VLSI test system ULTIMATE. 120–125.

Noda, Y., et al.. (2002). Evaluation of monolithic and segmented thermoelectric materials by using a large-temperature-span apparatus. 390–393. 2 indexed citations

Otsuji, Taiichi, et al.. (1988). Key technologies for 500-MHz VLSI test system ultimate. 108–113. 6 indexed citations

Yokoyama, K., M. Tomizawa, A. Yoshii, & T. Sudo. (1985). Semiconductor device simulation at NTT. IEEE Transactions on Electron Devices. 32(10). 2008–2017. 14 indexed citations

Takada, T., et al.. (1984). Analysis of High-Speed GaAs Source-Coupled FET Logic Circuits. IEEE Transactions on Microwave Theory and Techniques. 32(1). 5–10. 16 indexed citations

Suzuki, Masao, S. Horiguchi, & T. Sudo. (1983). A 5K-gate bipolar masterslice LSI with a 500 ps loaded gate delay. IEEE Journal of Solid-State Circuits. 18(5). 585–592. 14 indexed citations

Sudo, T.. (1982). Integrated DA System for Custom VLSI Design. Symposium on VLSI Technology. 68–71. 3 indexed citations

Tomizawa, Masaaki, Kiyoyuki Yokoyama, Akira Yoshii, & T. Sudo. (1982). Two-dimensional device simulator for gate level characterization. Solid-State Electronics. 25(9). 913–916. 8 indexed citations

Horiguchi, S., et al.. (1982). An automatically designed 32b CMOS VLSI processor. 54–55. 6 indexed citations

10.

Takada, T., et al.. (1982). A MESFET Variable-Capacitance Model for GaAs Integrated Circuit Simulation. IEEE Transactions on Microwave Theory and Techniques. 30(5). 719–724. 92 indexed citations

11.

Yoshii, A., et al.. (1982). A three-dimensional analysis of semiconductor devices. IEEE Transactions on Electron Devices. 29(2). 184–189. 47 indexed citations

12.

Yoshida, Kenji, et al.. (1981). Analysis and Definition of Overall Timing Accuracy in VLSI Test System.. International Test Conference. 7(3). 143–153. 8 indexed citations

13.

Tomizawa, M., et al.. (1981). An accurate design method of bipolar devices using a two-dimensional device simulator. IEEE Transactions on Electron Devices. 28(10). 1148–1153. 5 indexed citations

14.

Adachi, T., A. Yoshii, & T. Sudo. (1979). Two-dimensional semiconductor analysis using finite-element method. IEEE Transactions on Electron Devices. 26(7). 1026–1031. 28 indexed citations

15.

Sakai, T., et al.. (1979). Elevated electrode integrated circuits. IEEE Transactions on Electron Devices. 26(4). 379–385. 13 indexed citations

16.

Sakai, T., et al.. (1979). Elevated electrode integrated circuits. IEEE Journal of Solid-State Circuits. 14(2). 301–307. 3 indexed citations

17.

Sudo, T., et al.. (1978). A Subnanosecond Masterslice LSI Using Dielectric Isolation and Three Layer Metallization Technologies. Japanese Journal of Applied Physics. 17(S1). 19–19. 5 indexed citations

18.

Arita, Yoshinobu, K. Kato, & T. Sudo. (1977). The n⁺-IPOS scheme and its applications to IC's. IEEE Transactions on Electron Devices. 24(6). 756–757. 13 indexed citations

19.

Sudo, T., et al.. (1975). A monolithic 8 pJ/2 GHz logic family. IEEE Journal of Solid-State Circuits. 10(6). 524–529. 9 indexed citations

20.

Mizushima, Y. & T. Sudo. (1970). Surface-wave amplification between parallel semiconductors. IEEE Transactions on Electron Devices. 17(7). 541–549. 9 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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