D. Villeger

585 total citations
8 papers, 436 citations indexed

About

D. Villeger is a scholar working on Electrical and Electronic Engineering, Computational Theory and Mathematics and Hardware and Architecture. According to data from OpenAlex, D. Villeger has authored 8 papers receiving a total of 436 indexed citations (citations by other indexed papers that have themselves been cited), including 8 papers in Electrical and Electronic Engineering, 4 papers in Computational Theory and Mathematics and 3 papers in Hardware and Architecture. Recurrent topics in D. Villeger's work include Low-power high-performance VLSI design (8 papers), Numerical Methods and Algorithms (4 papers) and VLSI and FPGA Design Techniques (3 papers). D. Villeger is often cited by papers focused on Low-power high-performance VLSI design (8 papers), Numerical Methods and Algorithms (4 papers) and VLSI and FPGA Design Techniques (3 papers). D. Villeger collaborates with scholars based in United States and France. D. Villeger's co-authors include Vojin G. Oklobdzija and Shen-Iuan Liu and has published in prestigious journals such as IEEE Transactions on Computers, Electronics Letters and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In The Last Decade

D. Villeger

8 papers receiving 380 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
D. Villeger United States	6	382	197	148	103	64	8	436
E. Hökenek United States	8	280 0.7×	178 0.9×	259 1.8×	82 0.8×	115 1.8×	12	403
P.-M. Seidel United States	10	284 0.7×	143 0.7×	269 1.8×	74 0.7×	107 1.7×	25	353
Nikhil Jayakumar United States	12	361 0.9×	184 0.9×	114 0.8×	43 0.4×	43 0.7×	30	436
B. Ramkumar United States	6	235 0.6×	111 0.6×	120 0.8×	113 1.1×	25 0.4×	13	338
Jiun-Ping Wang Taiwan	5	278 0.7×	109 0.6×	120 0.8×	106 1.0×	42 0.7×	7	349
M.S. Schmookler United States	9	237 0.6×	147 0.7×	233 1.6×	44 0.4×	93 1.5×	13	319
Ted E. Williams United States	10	428 1.1×	355 1.8×	131 0.9×	64 0.6×	37 0.6×	13	548
A.M. Shams United States	10	619 1.6×	96 0.5×	183 1.2×	357 3.5×	114 1.8×	18	727
Zhixi Yang China	7	492 1.3×	147 0.7×	67 0.5×	195 1.9×	25 0.4×	16	533
Kahng United States	6	309 0.8×	151 0.8×	51 0.3×	53 0.5×	19 0.3×	9	355

Countries citing papers authored by D. Villeger

Since Specialization

Citations

This map shows the geographic impact of D. Villeger's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by D. Villeger with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites D. Villeger more than expected).

Fields of papers citing papers by D. Villeger

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by D. Villeger. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by D. Villeger. The network helps show where D. Villeger may publish in the future.

Co-authorship network of co-authors of D. Villeger

This figure shows the co-authorship network connecting the top 25 collaborators of D. Villeger. A scholar is included among the top collaborators of D. Villeger based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with D. Villeger. D. Villeger is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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8 of 8 papers shown

1.

Oklobdzija, Vojin G., et al.. (2003). Considerations for design of a complex multiplier. 34. 366–370. 2 indexed citations

2.

Villeger, D. & Vojin G. Oklobdzija. (2002). Analysis of Booth encoding efficiency in parallel multipliers using compressors for reduction of partial products. 781–784. 23 indexed citations

3.

Oklobdzija, Vojin G. & D. Villeger. (2002). Multiplier design utilizing improved column compression tree and optimized final adder in CMOS technology. 23. 209–212. 8 indexed citations

4.

Villeger, D., et al.. (2002). An ASIC macro cell multiplier for complex numbers. 34. 589–593. 4 indexed citations

5.

Oklobdzija, Vojin G., D. Villeger, & Shen-Iuan Liu. (1996). A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach. IEEE Transactions on Computers. 45(3). 294–306. 269 indexed citations

6.

Oklobdzija, Vojin G. & D. Villeger. (1995). Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 3(2). 292–301. 91 indexed citations

7.

Oklobdzija, Vojin G., et al.. (1994). An integrated multiplier for complex numbers. The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology. 7(3). 213–222. 15 indexed citations

8.

Villeger, D. & Vojin G. Oklobdzija. (1993). Evaluation of Booth encoding techniques for parallel multiplier implementation. Electronics Letters. 29(23). 2016–2017. 24 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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