K. Ishibashi

589 citations

28 papers · 387 indexed · h-index 11

Co-authors: Kensuke Osada Masanao Yamaoka Hiroyuki Mizuno Masahiko Miyamoto Hiroyuki Ohta Shuji Ikeda Toshiaki Yamanaka Susumu Narita
Topics: Low-power high-performance VLSI design (16 papers)Advancements in Semiconductor Devices and Circuit Design (14 papers)Semiconductor materials and devices (11 papers)
Cited by: Hardware and Architecture Electrical and Electronic Engineering Biomedical Engineering
Journals: IEEE Journal of Solid-State Circuits IEEE Transactions on Electron Devices IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Partner nations: Japan United States Germany

In The Last Decade

K. Ishibashi

27 papers receiving 361 citations

Peers

Countries citing papers authored by K. Ishibashi

Since Specialization

Citations

This map shows the geographic impact of K. Ishibashi's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by K. Ishibashi with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites K. Ishibashi more than expected).

Fields of papers citing papers by K. Ishibashi

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by K. Ishibashi. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by K. Ishibashi. The network helps show where K. Ishibashi may publish in the future.

Co-authorship network of co-authors of K. Ishibashi

This figure shows the co-authorship network connecting the top 25 collaborators of K. Ishibashi. A scholar is included among the top collaborators of K. Ishibashi based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with K. Ishibashi. K. Ishibashi is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	1.7kV trench IGBT with deep and separate floating p-layer designed for low loss, low EMI noise, and high reliability 2011 ·So Watanabe,(unknown),(unknown),K. Ishibashi,(unknown),(unknown),Takashi Harada,Katsuaki Saito	25
2	A dynamic clock skew compensation circuit technique for low power clock distribution 2005 ·(unknown),(unknown),K. Ishibashi	2
3	0.5V Asymmetric Three-Tr. Cell (ATC) DRAM Using 90nm Generic CMOS Logic Process 2005 ·(unknown),(unknown),Y. Itoh,K. Ishibashi	10
4	A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond 2004 ·Y. Komatsu,(unknown),(unknown),(unknown),K. Ishibashi	19
5	3-D Device Modeling for SRAM Soft-Error Immunity and Tolerance Analysis 2004 ·IEEE Transactions on Electron Devices ·Ken Yamaguchi,(unknown),Kensuke Osada,K. Ishibashi,(unknown)	6
6	Offset calibrating comparator array for 1.2-V, 6bit, 4-Gsample/s flash ADCs using 0.13μm generic CMOS technology 2004 ·Hironao Okada,(unknown),(unknown),T. Tsukada,K. Ishibashi	14
7	0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme 2004 ·IEEE Journal of Solid-State Circuits ·Masanao Yamaoka,Kensuke Osada,K. Ishibashi	53
8	A 25 mu m/sup 2/, new poly-Si PMOS load (PPL) SRAM cell having excellent soft error immunity 2003 ·Toshiaki Yamanaka,Takayuki Hashimoto,Norikazu Hashimoto,Takashi Nishida,(unknown),K. Ishibashi,Yoshio Sakai,K. Shimohigashi,Eiji Takeda	2
9	A 18 μA-standby-current 1.8 V 200 MHz microprocessor with self substrate-biased data-retention mode 2003 ·Hiroyuki Mizuno,K. Ishibashi,(unknown),(unknown),Susumu Narita,(unknown),Shuji Ikeda,(unknown)	4
10	A 3-cycle lock time delay-locked loop with a parallel phase detector for low power mobile systems 2003 ·M. Miyazaki,K. Ishibashi	1
11	A stacked split word-line (SSW) cell for low-voltage operation, large capacity, high speed SRAMs 2002 ·Shuji Ikeda,Kei Asayama,N. Hashimoto,(unknown),Yoshinori Yoshida,(unknown),Toshiaki Yamanaka,K. Ishibashi,S. Meguro	3
12	A 200 MHz 1.2 W 1.4 GFLOPS microprocessor with graphic operation unit 2002 ·(unknown),(unknown),K. Ishibashi,Shogo Nakano,(unknown),Kei Suzuki,M. Tachibana,Y. Totsuka,(unknown),(unknown),Takeshi Yamada,Toshihiro Hattori,Hiroshi Maejima,N. Nakagawa,Susumu Narita,(unknown),Yuichi Shimazaki,(unknown),(unknown),Atsushi Hasegawa	4
13	An automatic-power-save cache memory for low-power RISC processors 2002 ·Yuichi Shimazaki,K. Ishibashi,(unknown),Susumu Narita,(unknown),(unknown),(unknown),(unknown),Shinichi Yoshioka,S. Tamaki,Satoru Nagata,(unknown),(unknown)	2
14	A 300 MHz 4-Mb wave-pipeline CMOS SRAM using a multi-phase PLL 2002 ·K. Ishibashi,(unknown),H. Toyoshima,Masataka Minami,(unknown),(unknown),Toshiaki Yamanaka,(unknown),Takashi Nishida	2
15	A noise-immune GHz-clock distribution scheme using synchronous distributed oscillators 2002 ·Hiroyuki Mizuno,K. Ishibashi	21
16	A 1 V 100 MHz 10 mW cache using separated bit-line memory hierarchy and domino tag comparators 2002 ·Hiroyuki Mizuno,(unknown),Kensuke Osada,(unknown),(unknown),(unknown),K. Ishibashi,T. Kure	1
17	An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode 1999 ·IEEE Journal of Solid-State Circuits ·Hiroyuki Mizuno,K. Ishibashi,(unknown),Toshihiro Hattori,Susumu Narita,(unknown),Shuji Ikeda,(unknown)	55
18	A 1-V TFT-load SRAM using a two-step word-voltage method 1992 ·IEEE Journal of Solid-State Circuits ·K. Ishibashi,(unknown),(unknown),K. Sasaki	29
19	An alpha -immune, 2-V supply voltage SRAM using a polysilicon PMOS load cell 1990 ·IEEE Journal of Solid-State Circuits ·K. Ishibashi,Toshiaki Yamanaka,K. Shimohigashi	21
20	A 42ns 1Mb CMOS SRAM 1987 ·O. Minato,Takeshi Sasaki,(unknown),K. Ishibashi,(unknown),(unknown),Kinya Nishimura,Yoshio Sakai,S. Meguro,(unknown),T. Masuhara	4

About K. Ishibashi

K. Ishibashi is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Networks and Communications, having authored 28 papers that have together received 387 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (16 papers), Advancements in Semiconductor Devices and Circuit Design (14 papers) and Semiconductor materials and devices (11 papers). The work is most often cited by research in Hardware and Architecture (91 citations), Electrical and Electronic Engineering (376 citations) and Biomedical Engineering (54 citations). K. Ishibashi has collaborated with scholars based in Japan, United States and Germany. Frequent co-authors include Kensuke Osada, Masanao Yamaoka, Hiroyuki Mizuno, Masahiko Miyamoto, Hiroyuki Ohta, Shuji Ikeda, Toshiaki Yamanaka, Susumu Narita, K. Sasaki and K. Shimohigashi. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Electron Devices and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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