Juinn-Dar Huang

1000 total citations
96 papers, 693 citations indexed

About

Juinn-Dar Huang is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Juinn-Dar Huang has authored 96 papers receiving a total of 693 indexed citations (citations by other indexed papers that have themselves been cited), including 67 papers in Electrical and Electronic Engineering, 47 papers in Hardware and Architecture and 27 papers in Computer Networks and Communications. Recurrent topics in Juinn-Dar Huang's work include Embedded Systems Design Techniques (30 papers), Electrowetting and Microfluidic Technologies (24 papers) and Interconnection Networks and Systems (24 papers). Juinn-Dar Huang is often cited by papers focused on Embedded Systems Design Techniques (30 papers), Electrowetting and Microfluidic Technologies (24 papers) and Interconnection Networks and Systems (24 papers). Juinn-Dar Huang collaborates with scholars based in Taiwan, India and United States. Juinn-Dar Huang's co-authors include Chia‐Hung Liu, Jing-Yang Jou, Bhargab B. Bhattacharya, Sukanta Bhattacharjee, Sudip Roy, Jie-Hong R. Jiang, Yihang Chen, Jianyu Chen, Robert Wille and Yu-Hsiang Kao and has published in prestigious journals such as Electronics Letters, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In The Last Decade

Juinn-Dar Huang

84 papers receiving 667 citations

Peers

Countries citing papers authored by Juinn-Dar Huang

Since Specialization

Citations

This map shows the geographic impact of Juinn-Dar Huang's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Juinn-Dar Huang with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Juinn-Dar Huang more than expected).

Fields of papers citing papers by Juinn-Dar Huang

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Juinn-Dar Huang. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Juinn-Dar Huang. The network helps show where Juinn-Dar Huang may publish in the future.

Co-authorship network of co-authors of Juinn-Dar Huang

This figure shows the co-authorship network connecting the top 25 collaborators of Juinn-Dar Huang. A scholar is included among the top collaborators of Juinn-Dar Huang based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Juinn-Dar Huang. Juinn-Dar Huang is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	A Hardware-Friendly Alternative to Softmax Function and Its Efficient VLSI Implementation for Deep Learning Applications 2024 ·(unknown), (unknown), Yu-Hsiang Huang, (unknown), Juinn-Dar Huang	0
2	Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization 2022 ·ACM Transactions on Design Automation of Electronic Systems ·(unknown), (unknown), (unknown), Chien‐Nan Jimmy Liu, Juinn-Dar Huang	1
3	Efficient Circuit Structure Analysis for Automatic Behavioral Model Generation in Mixed-Signal System Simulation 2021 ·Electronics ·(unknown), (unknown), (unknown), Chien‐Nan Jimmy Liu, Juinn-Dar Huang, Jing-Yang Jou, (unknown), (unknown)	0
4	A Coarse-Grained Dual-Convolver Based CNN Accelerator with High Computing Resource Utilization 2020 ·Yi Lu, Yilin Wu, Juinn-Dar Huang	4
5	Forecast-Based Sample Preparation Algorithm for Unbalanced Splitting Correction on DMFBs 2019 ·(unknown), Yi-Ling Chen, (unknown), Juinn-Dar Huang	1
6	Storage-aware sample preparation using flow-based microfluidic Labs-on-Chip 2018 ·Sukanta Bhattacharjee, Robert Wille, Juinn-Dar Huang, Bhargab B. Bhattacharya	9
7	Volume-oriented sample preparation for reactant minimization on flow-based microfluidic biochips with multi-segment mixers 2015 ·Design, Automation, and Test in Europe ·(unknown), Chia‐Hung Liu, Juinn-Dar Huang	13
8	Reactant Minimization in Sample Preparation on Digital Microfluidic Biochips 2015 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Chia‐Hung Liu, (unknown), Juinn-Dar Huang	22
9	Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints 2014 ·Design, Automation, and Test in Europe ·Yihang Chen, Jianyu Chen, Juinn-Dar Huang	8
10	Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints 2014 ·Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014 ·Yihang Chen, Jianyu Chen, Juinn-Dar Huang	1
11	Sample preparation for many-reactant bioassay on DMFBs using common dilution operation sharing 2013 ·International Conference on Computer Aided Design ·Chia‐Hung Liu, (unknown), (unknown), Juinn-Dar Huang	27
12	Equivalence checking of scheduling with speculative code transformations in high-level synthesis 2011 ·Asia and South Pacific Design Automation Conference ·(unknown), (unknown), Juinn-Dar Huang, Jing-Yang Jou	17
13	Throughput optimization for latency-insensitive system with minimal queue insertion 2011 ·Asia and South Pacific Design Automation Conference ·Juinn-Dar Huang, Yihang Chen, (unknown)	2
14	CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture 2009 ·Asia and South Pacific Design Automation Conference ·(unknown), Juinn-Dar Huang	3
15	Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture 2009 ·Asia and South Pacific Design Automation Conference ·(unknown), (unknown), Juinn-Dar Huang	4
16	A multicycle communication architecture and synthesis flow for global interconnect resource sharing 2008 ·Asia and South Pacific Design Automation Conference ·Wei‐Sheng Huang, (unknown), Juinn-Dar Huang, (unknown)	7
17	ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping 2000 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Juinn-Dar Huang, Jing-Yang Jou, (unknown)	12
18	A variable partitioning algorithm of BDD for FPGA technology mapping 1997 ·IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ·(unknown), (unknown), Juinn-Dar Huang, (unknown)	1
19	An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping 1996 ·International Conference on Computer Aided Design ·Juinn-Dar Huang, Jing-Yang Jou, (unknown)	10
20	Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture 1995 ·International Conference on Computer Aided Design ·Juinn-Dar Huang, Jing-Yang Jou, (unknown)	20

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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