Jing-Yang Jou

1.3k total citations
114 papers, 901 citations indexed

About

Jing-Yang Jou is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Networks and Communications. According to data from OpenAlex, Jing-Yang Jou has authored 114 papers receiving a total of 901 indexed citations (citations by other indexed papers that have themselves been cited), including 83 papers in Hardware and Architecture, 67 papers in Electrical and Electronic Engineering and 28 papers in Computer Networks and Communications. Recurrent topics in Jing-Yang Jou's work include VLSI and Analog Circuit Testing (57 papers), VLSI and FPGA Design Techniques (38 papers) and Embedded Systems Design Techniques (37 papers). Jing-Yang Jou is often cited by papers focused on VLSI and Analog Circuit Testing (57 papers), VLSI and FPGA Design Techniques (38 papers) and Embedded Systems Design Techniques (37 papers). Jing-Yang Jou collaborates with scholars based in Taiwan, United States and Canada. Jing-Yang Jou's co-authors include Jacob A. Abraham, Juinn-Dar Huang, Yao‐Wen Chang, Iris Hui-Ru Jiang, Sy‐Yen Kuo, Bo‐Cheng Lai, Chien‐Nan Jimmy Liu, Liren Huang, Jie-Hong R. Jiang and Kwang‐Ting Cheng and has published in prestigious journals such as Proceedings of the IEEE, IEEE Transactions on Computers and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

In The Last Decade

Jing-Yang Jou

103 papers receiving 839 citations

Peers

Jing-Yang Jou

EEE

CNC

CTM

SOFTW

Steve Y-L Lin United States

TingTing Hwang Taiwan

Gert Goossens Belgium

Shyue-Kung Lu Taiwan

Farzan Fallah United States

M. Favalli Italy

Vincent J. Mooney United States

Leon Stok United States

Guy Bois Canada

T. Grotker Germany

Steve Y-L Lin United States

Jing-Yang Jou

1.1k ×1.9

469 ×0.8

EEE

505 ×1.7

CNC

171 ×1.0

CTM

52 ×0.5

SOFTW

Citations per year, relative to Jing-Yang Jou Jing-Yang Jou (= 1×) peers Steve Y-L Lin

Countries citing papers authored by Jing-Yang Jou

Since Specialization

Citations

This map shows the geographic impact of Jing-Yang Jou's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Jing-Yang Jou with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Jing-Yang Jou more than expected).

Fields of papers citing papers by Jing-Yang Jou

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Jing-Yang Jou. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Jing-Yang Jou. The network helps show where Jing-Yang Jou may publish in the future.

Co-authorship network of co-authors of Jing-Yang Jou

This figure shows the co-authorship network connecting the top 25 collaborators of Jing-Yang Jou. A scholar is included among the top collaborators of Jing-Yang Jou based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Jing-Yang Jou. Jing-Yang Jou is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Liu, Chien‐Nan Jimmy, et al.. (2021). Efficient Circuit Structure Analysis for Automatic Behavioral Model Generation in Mixed-Signal System Simulation. Electronics. 10(9). 1088–1088.

Lai, Bo‐Cheng, et al.. (2014). A learning-on-cloud power management policy for smart devices. International Conference on Computer Aided Design. 376–381. 3 indexed citations

Jou, Jing-Yang, Chia‐Hui Chang, & Hsin‐Min Wang. (2014). Proceedings of the 26th Conference on Computational Linguistics and Speech Processing (ROCLING 2014). International Conference on Computational Linguistics. 5 indexed citations

Huang, Juinn-Dar, et al.. (2011). Equivalence checking of scheduling with speculative code transformations in high-level synthesis. Asia and South Pacific Design Automation Conference. 497–502. 17 indexed citations

Chao, Mango C.-T., et al.. (2011). Design-for-debug layout adjustment for FIB probing and circuit editing. 1–9. 1 indexed citations

Liu, Chien‐Nan Jimmy, et al.. (2007). Observability Analysis on HDL Descriptions for Effective Functional Validation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26(8). 1509–1521. 2 indexed citations

Jou, Jing-Yang, et al.. (2004). Layout techniques for on-chip interconnect inductance reduction. Asia and South Pacific Design Automation Conference. 269–273. 1 indexed citations

Jou, Jing-Yang, et al.. (2004). On compliance test of on-chip bus for SOC. Asia and South Pacific Design Automation Conference. 328–333. 12 indexed citations

Liu, Chien‐Nan Jimmy, I‐Ling Chen, & Jing-Yang Jou. (2001). An efficient design-for-verification technique for HDLs. 103–108. 1 indexed citations

10.

Huang, Juinn-Dar, et al.. (2000). ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 8(4). 392–400. 12 indexed citations

11.

Jou, Jing-Yang, et al.. (1999). Two-level logic minimization for low power. ACM Transactions on Design Automation of Electronic Systems. 4(1). 52–69. 6 indexed citations

12.

Jou, Jing-Yang, et al.. (1999). Noise-constrained performance optimization by simultaneous gate and wire sizing based on Lagrangian relaxation. 90–95. 16 indexed citations

13.

Jou, Jing-Yang, et al.. (1997). A power modeling and characterization method for macrocells using structure information. International Conference on Computer Aided Design. 502–506. 8 indexed citations

14.

Jou, Jing-Yang, et al.. (1997). Power driven partial scan. 642–647. 2 indexed citations

15.

Huang, Juinn-Dar, et al.. (1996). An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. International Conference on Computer Aided Design. 13–17. 10 indexed citations

16.

Jou, Jing-Yang, et al.. (1996). A power modeling and characterization method for the CMOS standard cell library. International Conference on Computer Aided Design. 400–404. 10 indexed citations

17.

Huang, Juinn-Dar, et al.. (1995). Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. International Conference on Computer Aided Design. 359–363. 20 indexed citations

18.

Jou, Jing-Yang & Kwang‐Ting Cheng. (1995). Timing-Driven Partial Scan. IEEE Design & Test of Computers. 12(4). 52–52.

19.

Jou, Jing-Yang & Kwang‐Ting Cheng. (1995). Timing-driven partial scan. IEEE Design & Test of Computers. 12(4). 52–59. 8 indexed citations

20.

Jou, Jing-Yang, et al.. (1988). BECOME: behavior level circuit synthesis based on structure mapping. Design Automation Conference. 409–414. 6 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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