D. Edwards

842 total citations
36 papers, 555 citations indexed

About

D. Edwards is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, D. Edwards has authored 36 papers receiving a total of 555 indexed citations (citations by other indexed papers that have themselves been cited), including 33 papers in Electrical and Electronic Engineering, 26 papers in Hardware and Architecture and 11 papers in Computer Networks and Communications. Recurrent topics in D. Edwards's work include Low-power high-performance VLSI design (24 papers), VLSI and Analog Circuit Testing (15 papers) and Interconnection Networks and Systems (11 papers). D. Edwards is often cited by papers focused on Low-power high-performance VLSI design (24 papers), VLSI and Analog Circuit Testing (15 papers) and Interconnection Networks and Systems (11 papers). D. Edwards collaborates with scholars based in United Kingdom, United States and Greece. D. Edwards's co-authors include Steve Furber, W.J. Bainbridge, Jim Garside, Carl S. Byington, Aristides Efthymiou, Padmanabhan Balasubramanian, Jose Nunez‐Yanez, Luis A. Plana, Sam Taylor and John Bainbridge and has published in prestigious journals such as IEEE Transactions on Very Large Scale Integration (VLSI) Systems, The Computer Journal and IEEE Transactions on Consumer Electronics.

In The Last Decade

D. Edwards

32 papers receiving 527 citations

Author Peers

Peers are selected by citation overlap in the author's most active subfields. citations · hero ref

Author						Papers	Cites
D. Edwards	383	368	176	92	47	36	555
Taewhan Kim	641 1.7×	738 2.0×	360 2.0×	40 0.4×	29 0.6×	132	1.1k
Cédric Wilwert	132 0.3×	271 0.7×	181 1.0×	74 0.8×	21 0.4×	6	390
John A. Nestor	205 0.5×	355 1.0×	127 0.7×	42 0.5×	43 0.9×	29	420
Florian Kriebel	489 1.3×	333 0.9×	225 1.3×	23 0.3×	32 0.7×	38	608
Chong-Min Kyung	227 0.6×	195 0.5×	129 0.7×	20 0.2×	21 0.4×	49	396
Tim Tuan	874 2.3×	532 1.4×	271 1.5×	37 0.4×	42 0.9×	20	1.0k
Xabier Iturbe	301 0.8×	345 0.9×	220 1.3×	9 0.1×	30 0.6×	44	480
Ruzica Jevtić	245 0.6×	193 0.5×	62 0.4×	20 0.2×	42 0.9×	25	361
Eli Bozorgzadeh	534 1.4×	582 1.6×	364 2.1×	25 0.3×	27 0.6×	58	788
David W. Hightower	307 0.8×	204 0.6×	101 0.6×	37 0.4×	31 0.7×	11	383

Countries citing papers authored by D. Edwards

Since Specialization

Citations

This map shows the geographic impact of D. Edwards's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by D. Edwards with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites D. Edwards more than expected).

Fields of papers citing papers by D. Edwards

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by D. Edwards. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by D. Edwards. The network helps show where D. Edwards may publish in the future.

Co-authorship network of co-authors of D. Edwards

This figure shows the co-authorship network connecting the top 25 collaborators of D. Edwards. A scholar is included among the top collaborators of D. Edwards based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with D. Edwards. D. Edwards is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

Edwards, D., et al.. (2012). Redundant Logic Insertion and Latency Reduction in Self‐Timed Adders. VLSI design. 2012(1). 5 indexed citations

Edwards, D., et al.. (2010). A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths. Research Explorer (The University of Manchester). 24–34. 11 indexed citations

Edwards, D., et al.. (2009). Heterogeneously encoded dual-bit self-timed adder. 120–123.

Edwards, D., et al.. (2006). Software Visualisation Techniques Adapted and Extended for Asynchronous Hardware Design. 31. 347–356. 1 indexed citations

Edwards, D., et al.. (2006). Synthesising Heterogeneously Encoded Systems. 82. 138–149. 5 indexed citations

Plana, Luis A., Sam Taylor, & D. Edwards. (2006). Attacking control overhead to improve synthesised asynchronous circuit performance. Research Explorer (The University of Manchester). 703–710. 14 indexed citations

Byington, Carl S., et al.. (2005). Dynamic Modeling and Wear-Based Remaining Useful Life Prediction of High Power Clutch Systems. Tribology Transactions. 48(2). 208–217. 42 indexed citations

Efthymiou, Aristides, John Bainbridge, & D. Edwards. (2005). Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 13(12). 1384–1393. 12 indexed citations

Efthymiou, Aristides, John Bainbridge, & D. Edwards. (2005). Adding Testability to an Asynchronous Interconnect for GALS SoC. 20–23. 3 indexed citations

10.

Efthymiou, Aristides, Christos Sotiriou, & D. Edwards. (2004). Automatic scan insertion and pattern generation for asynchronous circuits. Design, Automation, and Test in Europe. 1. 10672. 5 indexed citations

11.

Efthymiou, Aristides, et al.. (2004). Automatic scan insertion and pattern generation for asynchronous circuits. Proceedings Design, Automation and Test in Europe Conference and Exhibition. 672–673. 6 indexed citations

12.

Edwards, D., et al.. (2003). A burst-mode oriented back-end for the Balsa synthesis system. 330–337. 9 indexed citations

13.

Bainbridge, W.J., et al.. (2003). Delay-insensitive, point-to-point interconnect using m-of-n codes. Research Explorer (The University of Manchester). 132–140. 80 indexed citations

14.

Chelcea, Tiberiu, et al.. (2002). A Burst-Mode Oriented Back-End for the Balsa Synthesis System. Design, Automation, and Test in Europe. 330–337. 16 indexed citations

15.

Edwards, D., et al.. (2002). A hybrid asynchronous system design environment. 91–98. 6 indexed citations

16.

Edwards, D., et al.. (1996). 1/4 " digital VCR PRML channel and servo processing. IEEE Transactions on Consumer Electronics. 42(3). 599–605. 2 indexed citations

17.

Edwards, D., et al.. (1995). An investigation of iterative routing algorithms. European Design Automation Conference. 91–96. 2 indexed citations

18.

Brown, Michael, et al.. (1994). An appreciation of simulated annealing to maze routing. European Design Automation Conference. 434–439. 3 indexed citations

19.

Stavridou, V., Howard Barringer, & D. Edwards. (1988). Formal specification and verification of hardware: a comparative case study. Design Automation Conference. 197–204. 12 indexed citations

20.

Edwards, D., et al.. (1987). A high performance routing engine. 793–799. 8 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact