David Lewis

2.1k total citations
47 papers, 1.3k citations indexed

About

David Lewis is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, David Lewis has authored 47 papers receiving a total of 1.3k indexed citations (citations by other indexed papers that have themselves been cited), including 37 papers in Electrical and Electronic Engineering, 28 papers in Hardware and Architecture and 8 papers in Computer Networks and Communications. Recurrent topics in David Lewis's work include Low-power high-performance VLSI design (26 papers), VLSI and FPGA Design Techniques (25 papers) and VLSI and Analog Circuit Testing (15 papers). David Lewis is often cited by papers focused on Low-power high-performance VLSI design (26 papers), VLSI and FPGA Design Techniques (25 papers) and VLSI and Analog Circuit Testing (15 papers). David Lewis collaborates with scholars based in Canada and United States. David Lewis's co-authors include Guy Lemieux, Jonathan Rose, Paul Chow, D.A. Johns, Robert J. Francis, D. H. Jones, Sunil K. Singh, Aneesh Aggarwal, Andy Lee and Paul Leventis and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Computers and Electronics Letters.

In The Last Decade

David Lewis

45 papers receiving 1.2k citations

Peers

Countries citing papers authored by David Lewis

Since Specialization

Citations

This map shows the geographic impact of David Lewis's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by David Lewis with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites David Lewis more than expected).

Fields of papers citing papers by David Lewis

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by David Lewis. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by David Lewis. The network helps show where David Lewis may publish in the future.

Co-authorship network of co-authors of David Lewis

This figure shows the co-authorship network connecting the top 25 collaborators of David Lewis. A scholar is included among the top collaborators of David Lewis based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with David Lewis. David Lewis is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Architectural enhancements in Stratix V™ 2013 ·David Lewis, (unknown), (unknown), (unknown), (unknown), Andy Lee, (unknown), Haiming Yu	50
2	A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs 2010 ·Doris Chen, Deshanand P. Singh, (unknown), David Lewis, (unknown), (unknown), Vaughn Betz	18
3	Field-programmable gate array architectures and algorithms optimized for implementing datapath circuits 2004 ·Jonathan Rose, David Lewis, Andy Ye	9
4	MAX II: A low-cost, high-performance LUT-based CPLD 2004 ·Paul Leventis, (unknown), Mike Hutton, David Lewis	7
5	Cyclone ™: a low-cost, high-performance FPGA. 2003 ·Paul Leventis, (unknown), (unknown), David Lewis, (unknown), Giles Powell, (unknown), (unknown), (unknown), John Costello	18
6	Routing and Logic Architecture 2003 ·Genetika ·David Lewis, Vaughn Betz, David Jefferson, Andy Lee, C. Lane, Paul Leventis, (unknown), (unknown), Bruce Pedersen, Giles Powell, (unknown), (unknown), Richard Cliff, Jonathan Rose	1
7	Sigma-delta based IIR filters 2002 ·D.A. Johns, David Lewis	3
8	Circuit design of routing switches 2002 ·Guy Lemieux, David Lewis	57
9	An accurate LNS arithmetic unit using interleaved memory function interpolator 2002 ·David Lewis	12
10	Optimization of field-programmable gate array logic block architecture for speed 2002 ·Sunil K. Singh, Jonathan Rose, David Lewis, Kevin Chung, Paul Chow	20
11	A field programmable accelerator for compiled-code applications 2002 ·David Lewis, (unknown), (unknown)	6
12	Interleaved memory function interpolators with application to an accurate LNS arithmetic unit 1994 ·IEEE Transactions on Computers ·David Lewis	70
13	Highly Selective "Analog" Filters Using Delta Sigma Based IIR Filtering. 1993 ·International Symposium on Circuits and Systems ·D.A. Johns, David Lewis, (unknown)	3
14	A compiled-code hardware accelerator for circuit simulation 1992 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·David Lewis	10
15	The effect of logic block architecture on FPGA performance 1992 ·IEEE Journal of Solid-State Circuits ·Sunil K. Singh, Jonathan Rose, Paul Chow, David Lewis	63
16	A hierarchical compiled code event-driven logic simulator 1991 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·David Lewis	60
17	Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency 1990 ·IEEE Journal of Solid-State Circuits ·Jonathan Rose, Robert J. Francis, David Lewis, Paul Chow	158
18	The effect of logic block complexity on area of programmable gate arrays 1989 ·Jonathan Rose, Robert J. Francis, Paul Chow, David Lewis	35
19	A Hardware Engine for Analogue Mode Simulation of MOS Digital Circuits 1985 ·Design Automation Conference ·David Lewis	2
20	Magnetic and electrical methods of non-destructive testing 1951 ·David Lewis	0

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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