Kevin Chung

565 total citations
13 papers, 383 citations indexed

About

Kevin Chung is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Networks and Communications. According to data from OpenAlex, Kevin Chung has authored 13 papers receiving a total of 383 indexed citations (citations by other indexed papers that have themselves been cited), including 13 papers in Hardware and Architecture, 12 papers in Electrical and Electronic Engineering and 1 paper in Computer Networks and Communications. Recurrent topics in Kevin Chung's work include VLSI and Analog Circuit Testing (10 papers), Low-power high-performance VLSI design (9 papers) and VLSI and FPGA Design Techniques (9 papers). Kevin Chung is often cited by papers focused on VLSI and Analog Circuit Testing (10 papers), Low-power high-performance VLSI design (9 papers) and VLSI and FPGA Design Techniques (9 papers). Kevin Chung collaborates with scholars based in Canada, United States and Venezuela. Kevin Chung's co-authors include Jonathan Rose, Robert J. Francis, Paul Chow, Alan Mishchenko, Sunil K. Singh, David Lewis, Robert K. Brayton, Lesley Shannon and Peter Jamieson and has published in prestigious journals such as IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ACM Transactions on Reconfigurable Technology and Systems and Design Automation Conference.

In The Last Decade

Kevin Chung

13 papers receiving 351 citations

Peers

Countries citing papers authored by Kevin Chung

Since Specialization

Citations

This map shows the geographic impact of Kevin Chung's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Kevin Chung with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Kevin Chung more than expected).

Fields of papers citing papers by Kevin Chung

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Kevin Chung. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Kevin Chung. The network helps show where Kevin Chung may publish in the future.

Co-authorship network of co-authors of Kevin Chung

This figure shows the co-authorship network connecting the top 25 collaborators of Kevin Chung. A scholar is included among the top collaborators of Kevin Chung based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Kevin Chung. Kevin Chung is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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13 of 13 papers shown

#	Work	Indexed citations
1	Analyzing System-Level Information’s Correlation to FPGA Placement 2013 ·ACM Transactions on Reconfigurable Technology and Systems ·(unknown), Lesley Shannon, Peter Jamieson, Kevin Chung	1
2	WireMap 2009 ·ACM Transactions on Reconfigurable Technology and Systems ·(unknown), (unknown), Kevin Chung, Alan Mishchenko	17
3	SmartOpt 2009 ·(unknown), (unknown), (unknown), (unknown), Kevin Chung, Alan Mishchenko, Robert K. Brayton	6
4	WireMap 2008 ·(unknown), (unknown), Kevin Chung, Alan Mishchenko	22
5	TEMPT: technology mapping for the exploration of FPGA architectures with hard-wired connections 2003 ·Kevin Chung, Jonathan Rose	2
6	Optimization of field-programmable gate array logic block architecture for speed 2002 ·Sunil K. Singh, Jonathan Rose, David Lewis, Kevin Chung, Paul Chow	20
7	Chortle: a technology mapping program for lookup table-based field programmable gate arrays 2002 ·Robert J. Francis, Jonathan Rose, Kevin Chung	47
8	The design of an SRAM-based field-programmable gate array. I. Architecture 1999 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Paul Chow, (unknown), Jonathan Rose, Kevin Chung, (unknown), (unknown)	67
9	The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout 1999 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Paul Chow, (unknown), Jonathan Rose, Kevin Chung, (unknown), (unknown)	69
10	Architecture and Synthesis of Field-Programmable Gate Arrays with Hard-wired Connections 1994 ·Kevin Chung	9
11	A high-speed FPGA using programmable mini-tiles 1993 ·Paul Chow, (unknown), Kevin Chung, (unknown), Jonathan Rose	6
12	TEMPT: technology mapping for the exploration of FPGA architectures with hard-wired connections 1992 ·Design Automation Conference ·Kevin Chung, Jonathan Rose	11
13	Chortle 1990 ·Robert J. Francis, Jonathan Rose, Kevin Chung	106

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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