Andy Ye
- Electrical and Electronic Engineering
- Hardware and Architecture top 5%
- Computer Networks and Communications top 10%
- Signal Processing
- Computer Vision and Pattern Recognition
- Co-authors
- Jonathan RosePeter JamiesonIan KuonJason LuuFarheen KhanFei YuanKenneth B. KentDavid Lewis
- Topics
- VLSI and FPGA Design Techniques (20 papers)Low-power high-performance VLSI design (19 papers)VLSI and Analog Circuit Testing (16 papers)
- Cited by
- Hardware and ArchitectureElectrical and Electronic EngineeringComputer Networks and Communications
- Journals
- IEEE Transactions on Very Large Scale Integration (VLSI) SystemsAnalog Integrated Circuits and Signal ProcessingCircuits Systems and Signal Processing
- Partner nations
- CanadaUnited States
In The Last Decade
Andy Ye
33 papers receiving 322 citations
Peers
Comparison fields: 5 of 30
- Electrical and Electronic Engineering 287
- Hardware and Architecture 241
- Computer Networks and Communications 64
- Signal Processing 19
- Computer Vision and Pattern Recognition 17
Countries citing papers authored by Andy Ye
This map shows the geographic impact of Andy Ye's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Andy Ye with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Andy Ye more than expected).
Fields of papers citing papers by Andy Ye
This network shows the impact of papers produced by Andy Ye. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Andy Ye. The network helps show where Andy Ye may publish in the future.
Co-authorship network of co-authors of Andy Ye
This figure shows the co-authorship network connecting the top 25 collaborators of Andy Ye. A scholar is included among the top collaborators of Andy Ye based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Andy Ye. Andy Ye is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 2 | |
| 2 | 1 | |
| 3 | 13 | |
| 4 | 7 | |
| 5 | 2 | |
| 6 | 6 | |
| 7 | 0 | |
| 8 | 1 | |
| 9 | 0 | |
| 10 | 11 | |
| 11 | 2 | |
| 12 | 1 | |
| 13 | 2 | |
| 14 | 2 | |
| 15 | 5 | |
| 16 | 1 | |
| 17 | 1 | |
| 18 | 140 | |
| 19 | 1 | |
| 20 | Field-programmable gate array architectures and algorithms optimized for implementing datapath circuits | 9 |
About Andy Ye
Andy Ye is a scholar working on Hardware and Architecture, Signal Processing and Electrical and Electronic Engineering, having authored 36 papers that have together received 342 indexed citations. Recurring topics across this work include VLSI and FPGA Design Techniques (20 papers), Low-power high-performance VLSI design (19 papers) and VLSI and Analog Circuit Testing (16 papers). The work is most often cited by research in Hardware and Architecture (241 citations), Electrical and Electronic Engineering (287 citations) and Computer Networks and Communications (64 citations). Andy Ye has collaborated with scholars based in Canada and United States. Frequent co-authors include Jonathan Rose, Peter Jamieson, Ian Kuon, Jason Luu, Farheen Khan, Fei Yuan, Kenneth B. Kent, David Lewis, Sridhar Krishnan and Ping Chen. Their work appears in journals such as IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Analog Integrated Circuits and Signal Processing and Circuits Systems and Signal Processing.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.