Chak-Wa Pui

469 total citations
18 papers, 352 citations indexed

About

Chak-Wa Pui is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Chak-Wa Pui has authored 18 papers receiving a total of 352 indexed citations (citations by other indexed papers that have themselves been cited), including 16 papers in Electrical and Electronic Engineering, 14 papers in Hardware and Architecture and 4 papers in Computer Networks and Communications. Recurrent topics in Chak-Wa Pui's work include VLSI and FPGA Design Techniques (15 papers), VLSI and Analog Circuit Testing (12 papers) and Low-power high-performance VLSI design (7 papers). Chak-Wa Pui is often cited by papers focused on VLSI and FPGA Design Techniques (15 papers), VLSI and Analog Circuit Testing (12 papers) and Low-power high-performance VLSI design (7 papers). Chak-Wa Pui collaborates with scholars based in Hong Kong, China and Sweden. Chak-Wa Pui's co-authors include Evangeline F. Y. Young, Gengjie Chen, Wing-Kai Chow, Bei Yu, Jinwei Liu, Yuzhe Ma, Jian Kuang, Haocheng Li, Hang Zhang and Jingsong Chen and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ACM Transactions on Design Automation of Electronic Systems and Rare & Special e-Zone (The Hong Kong University of Science and Technology).

In The Last Decade

Chak-Wa Pui

17 papers receiving 343 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Chak-Wa Pui Hong Kong	10	321	280	71	23	12	18	352
David Papa United States	10	504 1.6×	397 1.4×	59 0.8×	11 0.5×	16 1.3×	22	532
Mike Hutton United States	9	249 0.8×	231 0.8×	41 0.6×	9 0.4×	36 3.0×	35	300
Eddie Hung Canada	11	227 0.7×	258 0.9×	48 0.7×	37 1.6×	14 1.2×	28	311
Christopher Lavin United States	10	296 0.9×	310 1.1×	112 1.6×	9 0.4×	29 2.4×	18	365
Yuejian Wu Canada	10	289 0.9×	263 0.9×	23 0.3×	7 0.3×	17 1.4×	28	318
Kuo-Liang Cheng Taiwan	11	339 1.1×	337 1.2×	67 0.9×	10 0.4×	10 0.8×	23	388
Desmond A. Kirkpatrick United States	9	472 1.5×	309 1.1×	117 1.6×	5 0.2×	7 0.6×	20	512
Vidya Rajagopalan United States	5	109 0.3×	205 0.7×	150 2.1×	19 0.8×	13 1.1×	7	258
Gabriel L. Nazar Brazil	10	252 0.8×	203 0.7×	88 1.2×	14 0.6×	25 2.1×	58	307

Countries citing papers authored by Chak-Wa Pui

Since Specialization

Citations

This map shows the geographic impact of Chak-Wa Pui's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Chak-Wa Pui with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Chak-Wa Pui more than expected).

Fields of papers citing papers by Chak-Wa Pui

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Chak-Wa Pui. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Chak-Wa Pui. The network helps show where Chak-Wa Pui may publish in the future.

Co-authorship network of co-authors of Chak-Wa Pui

This figure shows the co-authorship network connecting the top 25 collaborators of Chak-Wa Pui. A scholar is included among the top collaborators of Chak-Wa Pui based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Chak-Wa Pui. Chak-Wa Pui is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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18 of 18 papers shown

Pui, Chak-Wa, et al.. (2023). TOFU: A Two-Step Floorplan Refinement Framework for Whitespace Reduction. 1–5. 2 indexed citations

Ye, Junjie, Chak-Wa Pui, Guangliang Zhang, et al.. (2022). Heterogeneous Graph Neural Network-Based Imitation Learning for Gate Sizing Acceleration. 1–9. 11 indexed citations

Zheng, Daniel, Xiaopeng Zhang, Chak-Wa Pui, & Evangeline F. Y. Young. (2021). Multi-FPGA Co-optimization. 176–182. 3 indexed citations

Liu, Jinwei, et al.. (2020). CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model. 1–6. 59 indexed citations

Pui, Chak-Wa & Evangeline F. Y. Young. (2020). Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems. ACM Transactions on Design Automation of Electronic Systems. 25(2). 1–23. 5 indexed citations

Xu, Biying, Shaolan Li, Chak-Wa Pui, et al.. (2019). Device Layer-Aware Analytical Placement for Analog Circuits. 19–26. 18 indexed citations

Chen, Gengjie, Chak-Wa Pui, Haocheng Li, & Evangeline F. Y. Young. (2019). Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39(9). 1902–1915. 28 indexed citations

Chen, Gengjie, et al.. (2019). Detailed routing by sparse grid graph and minimum-area-captured path search. 754–760. 24 indexed citations

Pui, Chak-Wa & Evangeline F. Y. Young. (2019). Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems. 1–8. 2 indexed citations

10.

Pui, Chak-Wa, et al.. (2019). Simultaneous Reconnection Surgery Technique of Routing With Machine Learning-Based Acceleration. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39(6). 1245–1257. 4 indexed citations

11.

Pui, Chak-Wa, Gang Wu, Freddy Y. C. Mang, & Evangeline F. Y. Young. (2019). An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems. 7 indexed citations

12.

Pui, Chak-Wa, et al.. (2018). A two-step search engine for large scale boolean matching under NP3 equivalence. Asia and South Pacific Design Automation Conference. 592–598.

13.

Pui, Chak-Wa, et al.. (2018). A two-step search engine for large scale boolean matching under NP3 equivalence. 3. 592–598. 2 indexed citations

14.

Pui, Chak-Wa, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, & Bei Yu. (2017). Clock-aware ultrascale FPGA placement with machine learning routability prediction. International Conference on Computer Aided Design. 21 indexed citations

15.

Chen, Gengjie, Chak-Wa Pui, Wing-Kai Chow, et al.. (2017). RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 37(10). 2022–2035. 41 indexed citations

16.

Pui, Chak-Wa, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, & Bei Yu. (2017). Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper). Rare & Special e-Zone (The Hong Kong University of Science and Technology). 38 indexed citations

17.

Pui, Chak-Wa, Gengjie Chen, Wing-Kai Chow, et al.. (2016). RippleFPGA. 1–8. 47 indexed citations

18.

Chow, Wing-Kai, Chak-Wa Pui, & Evangeline F. Y. Young. (2016). Legalization algorithm for multiple-row height standard cell design. 1–6. 40 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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