Chak-Wa Pui

469 citations

18 papers · 352 indexed · h-index 10

Hardware and Architecture top 2%
- VLSI and Analog Circuit Testing 12
Electrical and Electronic Engineering top 10%
- VLSI and FPGA Design Techniques 15
- Low-power high-performance VLSI design 7
- 3D IC and TSV technologies 4
- Advancements in Photolithography Techniques 2
Computer Networks and Communications top 10%
- Interconnection Networks and Systems 4
Software
- Software Testing and Debugging Techniques 2
Computer Graphics and Computer-Aided Design
Computational Theory and Mathematics
- Formal Methods in Verification 2

Co-authors: Evangeline F. Y. Young Gengjie Chen Wing-Kai Chow Bei Yu Jinwei Liu Yuzhe Ma Jian Kuang Haocheng Li
Cited by: Hardware and Architecture Electrical and Electronic Engineering Computer Networks and Communications
Journals: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (3 papers)ACM Transactions on Design Automation of Electronic Systems (1 paper)Rare & Special e-Zone (The Hong Kong University of Science and Technology) (1 paper)
Partner nations: Hong Kong China Sweden

In The Last Decade

Chak-Wa Pui

17 papers receiving 343 citations

Peers

Countries citing papers authored by Chak-Wa Pui

Since Specialization

Citations

This map shows the geographic impact of Chak-Wa Pui's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Chak-Wa Pui with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Chak-Wa Pui more than expected).

Fields of papers citing papers by Chak-Wa Pui

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Chak-Wa Pui. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Chak-Wa Pui. The network helps show where Chak-Wa Pui may publish in the future.

Co-authorship network

The 25 scholars most cited alongside Chak-Wa Pui, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Chak-Wa Pui Line = papers co-authored together Chak-Wa Pui links everyone, so they are left out of the graph.

All Works

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18 of 18 papers shown

#	Work
1	TOFU: A Two-Step Floorplan Refinement Framework for Whitespace Reduction Ruby Chang,Chak-Wa Pui,Fangzhou Wang,Kenneth Ngo,Naoaki MIYAGAWA,Yu Huang,H. R. Lee	2023	2
2	Heterogeneous Graph Neural Network-Based Imitation Learning for Gate Sizing Acceleration مولود نورين,Junjie Ye,Chak-Wa Pui,Yuanchang Ye,Guangliang Zhang,Bin Wang,Jianye Hao,Guangyong Chen,Pheng‐Ann Heng	2022	11
3	Multi-FPGA Co-optimization Daniel Zheng,Xiaopeng Zhang,Chak-Wa Pui,Evangeline F. Y. Young	2021	3
4	CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model Jinwei Liu,Chak-Wa Pui,P.A.J.M. Coppen,Evangeline F. Y. Young	2020	59
5	Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems ACM Transactions on Design Automation of Electronic Systems ·Chak-Wa Pui,Evangeline F. Y. Young	2020	5
6	Device Layer-Aware Analytical Placement for Analog Circuits Biying Xu,Shaolan Li,Chak-Wa Pui,Osguner,Linxiao Shen,Yibo Lin,Nan Sun,David Z. Pan	2019	18
7	Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Gengjie Chen,Chak-Wa Pui,Haocheng Li,Evangeline F. Y. Young	2019	28
8	Detailed routing by sparse grid graph and minimum-area-captured path search Gengjie Chen,Chak-Wa Pui,Haocheng Li,Jingsong Chen,Drs Funaki,Evangeline F. Y. Young	2019	24
9	Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems Chak-Wa Pui,Evangeline F. Y. Young	2019	2
10	Simultaneous Reconnection Surgery Technique of Routing With Machine Learning-Based Acceleration IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Teti Widia Komarawati,Chak-Wa Pui,Evangeline F. Y. Young	2019	4
11	An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems Chak-Wa Pui,Gang Wu,Freddy Y. C. Mang,Evangeline F. Y. Young	2019	7
12	A two-step search engine for large scale boolean matching under NP3 equivalence Asia and South Pacific Design Automation Conference ·Chak-Wa Pui,Teti Widia Komarawati,Haocheng Li,Gengjie Chen,Evangeline F. Y. Young	2018	0
13	A two-step search engine for large scale boolean matching under NP3 equivalence Chak-Wa Pui,Teti Widia Komarawati,Haocheng Li,Gengjie Chen,Evangeline F. Y. Young	2018	2
14	Clock-aware ultrascale FPGA placement with machine learning routability prediction International Conference on Computer Aided Design ·Chak-Wa Pui,Gengjie Chen,Yuzhe Ma,Evangeline F. Y. Young,Bei Yu	2017	21
15	RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Gengjie Chen,Chak-Wa Pui,Wing-Kai Chow,百番星,Jian Kuang,Evangeline F. Y. Young,Bei Yu	2017	41
16	Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper) Rare & Special e-Zone (The Hong Kong University of Science and Technology) ·Chak-Wa Pui,Gengjie Chen,Yuzhe Ma,Evangeline F. Y. Young,Bei Yu	2017	38
17	RippleFPGA Chak-Wa Pui,Gengjie Chen,Wing-Kai Chow,百番星,Jian Kuang,Teti Widia Komarawati,Hang Zhang,Evangeline F. Y. Young,Bei Yu	2016	47
18	Legalization algorithm for multiple-row height standard cell design Wing-Kai Chow,Chak-Wa Pui,Evangeline F. Y. Young	2016	40

About Chak-Wa Pui

Chak-Wa Pui is a scholar working on Hardware and Architecture, Software and Computer Graphics and Computer-Aided Design, having authored 18 papers that have together received 352 indexed citations. Recurring topics across this work include VLSI and FPGA Design Techniques (15 papers), VLSI and Analog Circuit Testing (12 papers), Low-power high-performance VLSI design (7 papers), 3D IC and TSV technologies (4 papers), Interconnection Networks and Systems (4 papers), Advancements in Photolithography Techniques (2 papers), Software Testing and Debugging Techniques (2 papers) and Formal Methods in Verification (2 papers). The work is most often cited by research in Hardware and Architecture (280 citations), Electrical and Electronic Engineering (321 citations) and Computer Networks and Communications (71 citations). Chak-Wa Pui has collaborated with scholars based in Hong Kong, China and Sweden. Frequent co-authors include Evangeline F. Y. Young, Gengjie Chen, Wing-Kai Chow, Bei Yu, Jinwei Liu, Yuzhe Ma, Jian Kuang, Haocheng Li, Hang Zhang and Jingsong Chen. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ACM Transactions on Design Automation of Electronic Systems, Rare & Special e-Zone (The Hong Kong University of Science and Technology), International Conference on Computer Aided Design and Asia and South Pacific Design Automation Conference.

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