Biying Xu

628 citations

21 papers · 471 indexed · h-index 13

Electrical and Electronic Engineering top 10%
Hardware and Architecture top 5%
Biomedical Engineering
Artificial Intelligence
Industrial and Manufacturing Engineering top 10%

Co-authors: David Z. Pan Nan Sun Shaolan Li Xiyuan Tang Yibo Lin Keren Zhu Linxiao Shen Mingjie Liu
Topics: VLSI and FPGA Design Techniques (11 papers)VLSI and Analog Circuit Testing (10 papers)Advancements in Photolithography Techniques (7 papers)
Cited by: Hardware and Architecture Electrical and Electronic Engineering Industrial and Manufacturing Engineering
Journals: PLoS ONE IEEE Journal of Solid-State Circuits IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Partner nations: United States Hong Kong China

In The Last Decade

Biying Xu

21 papers receiving 463 citations

Peers

Countries citing papers authored by Biying Xu

Since Specialization

Citations

This map shows the geographic impact of Biying Xu's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Biying Xu with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Biying Xu more than expected).

Fields of papers citing papers by Biying Xu

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Biying Xu. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Biying Xu. The network helps show where Biying Xu may publish in the future.

Co-authorship network of co-authors of Biying Xu

This figure shows the co-authorship network connecting the top 25 collaborators of Biying Xu. A scholar is included among the top collaborators of Biying Xu based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Biying Xu. Biying Xu is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Vision-based quality evaluation method towards automated penetrant testing 2025 ·NDT & E International ·(unknown),Tian Xu,(unknown),Biying Xu,Hegao Cai,Jie Zhao	2
2	MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII 2020 ·IEEE Design and Test ·(unknown),(unknown),Biying Xu,Keren Zhu,Xiyuan Tang,Shaolan Li,Yibo Lin,Nan Sun,David Z. Pan	48
3	Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis 2020 ·(unknown),Keren Zhu,Xiyuan Tang,Biying Xu,Wei Shi,Nan Sun,David Z. Pan	18
4	S³DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity 2020 ·(unknown),Wuxi Li,Keren Zhu,Biying Xu,Yibo Lin,Linxiao Shen,Xiyuan Tang,Nan Sun,David Z. Pan	25
5	A 0.025-mm² 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-$\Delta\Sigma$ M Structure 2019 ·IEEE Journal of Solid-State Circuits ·Wenda Zhao,Shaolan Li,Biying Xu,Xiangxing Yang,Xiyuan Tang,Linxiao Shen,Nanshu Lu,David Z. Pan,Nan Sun	49
6	Device Layer-Aware Analytical Placement for Analog Circuits 2019 ·Biying Xu,Shaolan Li,Chak-Wa Pui,(unknown),Linxiao Shen,Yibo Lin,Nan Sun,David Z. Pan	18
7	Hardware-software co-design of slimmed optical neural networks 2019 ·Zheng Zhao,Derong Liu,(unknown),Zhoufeng Ying,(unknown),Biying Xu,Bei Yu,Ray T. Chen,David Z. Pan	34
8	WellGAN 2019 ·Biying Xu,Yibo Lin,Xiyuan Tang,Shaolan Li,Linxiao Shen,Nan Sun,David Z. Pan	45
9	GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance 2019 ·Keren Zhu,Mingjie Liu,Yibo Lin,Biying Xu,Shaolan Li,Xiyuan Tang,Nan Sun,David Z. Pan	48
10	A 1-GS/s 20 MHz-BW Capacitive-Input Continuous-Time $\Delta\Sigma$ ADC Using a Novel Parasitic Pole-Mitigated Fully Differential VCO 2019 ·IEEE Solid-State Circuits Letters ·Abhishek Mukherjee,(unknown),Biying Xu,Shaolan Li,Linxiao Shen,Xiyuan Tang,David Z. Pan,Nan Sun	8
11	Exploiting Wavelength Division Multiplexing for Optical Logic Synthesis 2019 ·Zheng Zhao,(unknown),Zhoufeng Ying,Biying Xu,Chenghao Feng,Ray T. Chen,David Z. Pan	8
12	A 0.025-mm² 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure 2019 ·Shaolan Li,Wenda Zhao,Biying Xu,Xiangxing Yang,Xiyuan Tang,Linxiao Shen,Nanshu Lu,David Z. Pan,Nan Sun	16
13	MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper 2019 ·Biying Xu,Keren Zhu,Mingjie Liu,Yibo Lin,Shaolan Li,Xiyuan Tang,Nan Sun,David Z. Pan	53
14	Analog Placement Constraint Extraction and Exploration with the Application to Layout Retargeting 2018 ·Biying Xu,(unknown),(unknown),David Z. Pan	6
15	Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict 2017 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Yibo Lin,Bei Yu,Biying Xu,David Z. Pan	9
16	Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits 2017 ·Biying Xu,Shaolan Li,Xiaoqing Xu,Nan Sun,David Z. Pan	19
17	A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology 2017 ·Biying Xu,Shaolan Li,Nan Sun,David Z. Pan	23
18	Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict 2015 ·International Conference on Computer Aided Design ·Yibo Lin,Bei Yu,Biying Xu,David Z. Pan	6
19	Triple patterning aware detailed placement toward zero cross-row middle-of-line conflict 2015 ·Yibo Lin,Bei Yu,Biying Xu,David Z. Pan	8
20	Improving Google Flu Trends Estimates for the United States through Transformation 2014 ·PLoS ONE ·Leah J. Martin,Biying Xu,Yutaka Yasui	18

About Biying Xu

Biying Xu is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Industrial and Manufacturing Engineering, having authored 21 papers that have together received 471 indexed citations. Recurring topics across this work include VLSI and FPGA Design Techniques (11 papers), VLSI and Analog Circuit Testing (10 papers) and Advancements in Photolithography Techniques (7 papers). The work is most often cited by research in Hardware and Architecture (168 citations), Electrical and Electronic Engineering (395 citations) and Industrial and Manufacturing Engineering (30 citations). Biying Xu has collaborated with scholars based in United States, Hong Kong and China. Frequent co-authors include David Z. Pan, Nan Sun, Shaolan Li, Xiyuan Tang, Yibo Lin, Keren Zhu, Linxiao Shen, Mingjie Liu, Bei Yu and Nanshu Lu. Their work appears in journals such as PLoS ONE, IEEE Journal of Solid-State Circuits and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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