C. Russ

853 total citations
36 papers, 645 citations indexed

About

C. Russ is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Bioengineering. According to data from OpenAlex, C. Russ has authored 36 papers receiving a total of 645 indexed citations (citations by other indexed papers that have themselves been cited), including 36 papers in Electrical and Electronic Engineering, 3 papers in Biomedical Engineering and 1 paper in Bioengineering. Recurrent topics in C. Russ's work include Semiconductor materials and devices (31 papers), Electrostatic Discharge in Electronics (31 papers) and Integrated Circuits and Semiconductor Failure Analysis (21 papers). C. Russ is often cited by papers focused on Semiconductor materials and devices (31 papers), Electrostatic Discharge in Electronics (31 papers) and Integrated Circuits and Semiconductor Failure Analysis (21 papers). C. Russ collaborates with scholars based in Germany, United States and Belgium. C. Russ's co-authors include K. Verhaege, M. Mergens, J. Armer, P. Jozwiak, B. Keppens, G. Groeseneken, Karlheinz Bock, S. Thijs, D. Linten and Mirko Scholz and has published in prestigious journals such as IEEE Transactions on Electron Devices, Microelectronics Reliability and IEEE Transactions on Device and Materials Reliability.

In The Last Decade

C. Russ

36 papers receiving 590 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
C. Russ Germany	16	643	26	17	4	2	36	645
H. Brut France	8	263 0.4×	35 1.3×	18 1.1×	10 2.5×		15	264
Stephen G. Beebe United States	11	316 0.5×	34 1.3×	11 0.6×	10 2.5×		30	321
Guido Notermans Netherlands	10	297 0.5×	11 0.4×	13 0.8×	5 1.3×		37	304
Hae-Kang Jung South Korea	12	301 0.5×	38 1.5×	20 1.2×	3 0.8×		22	305
Fumio Yuki Japan	11	367 0.6×	56 2.2×	38 2.2×	14 3.5×	1 0.5×	28	374
S.B. Anand United States	5	207 0.3×	50 1.9×	11 0.6×	2 0.5×		8	209
Paolo Madoglio United States	9	297 0.5×	111 4.3×	9 0.5×	4 1.0×		16	300
Hidemi Noguchi Japan	9	191 0.3×	29 1.1×	8 0.5×	7 1.8×		32	191
Ariel Cohen Israel	7	256 0.4×	65 2.5×	31 1.8×	3 0.8×		12	265
Woo-Seop Kim South Korea	7	146 0.2×	18 0.7×	18 1.1×	7 1.8×		20	151

Countries citing papers authored by C. Russ

Since Specialization

Citations

This map shows the geographic impact of C. Russ's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by C. Russ with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites C. Russ more than expected).

Fields of papers citing papers by C. Russ

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by C. Russ. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by C. Russ. The network helps show where C. Russ may publish in the future.

Co-authorship network of co-authors of C. Russ

This figure shows the co-authorship network connecting the top 25 collaborators of C. Russ. A scholar is included among the top collaborators of C. Russ based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with C. Russ. C. Russ is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Thijs, S., Mirko Scholz, D. Linten, et al.. (2010). SCCF — System to component level correlation factor. Electrical Overstress/Electrostatic Discharge Symposium. 1–10. 12 indexed citations

Chatty, Kiran, et al.. (2008). Investigation of ESD performance of silicide-blocked stacked NMOSFETs in a 45nm bulk CMOS technology. 304–312. 8 indexed citations

Thijs, S., C. Russ, David Trémouilles, et al.. (2008). Design methodology of FinFET devices that meet IC-Level HBM ESD targets. 294–302. 9 indexed citations

Fulde, M., K. von Arnim, C. Pacha, et al.. (2007). Advances in Multi-Gate MOSFET Circuit Design. 186–189. 5 indexed citations

Chatty, Kiran, et al.. (2007). Process and design optimization of a protection scheme based on NMOSFETs with ESD implant in 65nm and 45nm CMOS technologies. 7A.2–1. 18 indexed citations

Trémouilles, David, S. Thijs, C. Russ, et al.. (2007). Understanding the optimization of sub-45nm FinFET devices for ESD applications. 7A.5–1. 22 indexed citations

Knoblinger, G., F. Kuttner, Andrew Marshall, et al.. (2006). Design and Evaluation of Basic Analog Circuits in an Emerging MuGFET Technology. 37–40. 21 indexed citations

Pacha, C., K. von Arnim, T. Schulz, et al.. (2006). Circuit design issues in multi-gate FET CMOS technologies. 1656–1665. 23 indexed citations

Li, Junjun, Robert Gauthier, Kiran Chatty, et al.. (2005). PMOSFET-based ESD protection in 65nm bulk CMOS technology for improved external latchup robustness. Electrical Overstress/Electrostatic Discharge Symposium. 1–8. 11 indexed citations

10.

Russ, C., K. Verhaege, Karlheinz Bock, et al.. (2005). A compact model for the grounded-gate nMOS behaviour under CDM ESD stress. 29. 302–315. 16 indexed citations

11.

Russ, C.. (2005). Foreword Special Section on Electrical Overstress/Electrostatic Discharge (EOS/ESD). IEEE Transactions on Electronics Packaging Manufacturing. 28(3). 205–205. 1 indexed citations

12.

Mergens, M., Benjamin Van Camp, B. Keppens, et al.. (2005). ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies. 1194–1197. 14 indexed citations

13.

Goßner, Harald, K. Domański, Kai Esmark, et al.. (2005). SoC — A real challenge for ESD protection?. 1–10. 2 indexed citations

14.

Mergens, M., C. Russ, K. Verhaege, et al.. (2004). Diode-triggered SCR (DTSCR) for RF-ESD protection of BiCMOS SiGe HBTs and CMOS ultra-thin gate oxides. 21.3.1–21.3.4. 84 indexed citations

15.

Keppens, B., M. Mergens, J. Armer, et al.. (2003). Active-area-segmentation (AAS) technique for compact, ESD robust, fully silicided NMOS design. Electrical Overstress/Electrostatic Discharge Symposium. 1–9. 17 indexed citations

16.

Mergens, M., K. Verhaege, C. Russ, et al.. (2003). Multi-finger turn-on circuits and design techniques for enhanced ESD performance and width scaling. Microelectronics Reliability. 43(9-11). 1537–1543. 10 indexed citations

17.

Russ, C., et al.. (2001). GGSCRs: GGNMOS Triggered silicon controlled rectifiers for ESD protection in deep sub-micron CMOS processes. Electrical Overstress/Electrostatic Discharge Symposium. 22–31. 61 indexed citations

18.

Mergens, M., et al.. (2001). Multi-finger turn-on circuits and design techniques for enhanced ESD performance and width-scaling. Electrical Overstress/Electrostatic Discharge Symposium. 1–11. 35 indexed citations

19.

Verhaege, K., et al.. (1997). Grounded-gate nMOS transistor behavior under CDM ESD stress conditions. IEEE Transactions on Electron Devices. 44(11). 1972–1980. 23 indexed citations

20.

Verhaege, K., et al.. (1996). Justifications for reducing HBM and MM ESD qualification test time. Microelectronics Reliability. 36(11-12). 1715–1718. 4 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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