Sarvesh Bhardwaj

1.5k citations

31 papers · 1.2k indexed · h-index 14

Hardware and Architecture top 2%
- VLSI and Analog Circuit Testing 7
- Parallel Computing and Optimization Techniques 6
Electrical and Electronic Engineering top 5%
- Low-power high-performance VLSI design 22
- VLSI and FPGA Design Techniques 11
- Advancements in Semiconductor Devices and Circuit Design 9
- Radiation Effects in Electronics 5
- Advanced Memory and Neural Computing 4
Statistics, Probability and Uncertainty top 5%
- Probabilistic and Robust Engineering Design 4
Computer Networks and Communications top 10%
Computational Theory and Mathematics

Co-authors: Sarma Vrudhula Yu Cao Wenping Wang Rakesh Vattikonda Frank Liu Shengqi Yang Praveen Ghanta David Blaauw
Cited by: Hardware and Architecture Electrical and Electronic Engineering Statistics, Probability and Uncertainty
Journals: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (4 papers)IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2 papers)DSpace - NTUA (National Technical University of Athens) (1 paper)
Partner nations: United States Switzerland Hungary

In The Last Decade

Sarvesh Bhardwaj

31 papers receiving 1.1k citations

Peers

Countries citing papers authored by Sarvesh Bhardwaj

Since Specialization

Citations

This map shows the geographic impact of Sarvesh Bhardwaj's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Sarvesh Bhardwaj with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Sarvesh Bhardwaj more than expected).

Fields of papers citing papers by Sarvesh Bhardwaj

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Sarvesh Bhardwaj. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Sarvesh Bhardwaj. The network helps show where Sarvesh Bhardwaj may publish in the future.

Co-authorship network

The 25 scholars most cited alongside Sarvesh Bhardwaj, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Sarvesh Bhardwaj Line = papers co-authored together Sarvesh Bhardwaj links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Ankur Sharma,David Chinnery,T. Reimann,Sarvesh Bhardwaj,Chris Chu	2019	19
2	Fast Lagrangian Relaxation based gate sizing using multi-threading Ankur Sharma,David Chinnery,Sarvesh Bhardwaj,Chris Chu	2015	12
3	On Timing Closure Pei-Ci Wu,Martin D. F. Wong,Ivailo Nedelchev,Sarvesh Bhardwaj,Vidyamani Parkhe	2014	11
4	Reducing Functional Unit Power Consumption and its Variation Using Leakage Sensors IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Aviral Shrivastava,Deepa Kannan,Sarvesh Bhardwaj,Sarma Vrudhula	2009	4
5	The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Wenping Wang,Shengqi Yang,Sarvesh Bhardwaj,Sarma Vrudhula,Frank Liu,Yu Cao	2009	218
6	Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Sarvesh Bhardwaj,Sarma Vrudhula	2008	13
7	A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations Sarvesh Bhardwaj,Sarma Vrudhula	2007	4
8	Predictive Modeling of the NBTI Effect for Reliable Design Sarvesh Bhardwaj,Wenping Wang,Rakesh Vattikonda,Yu Cao,Sarma Vrudhula	2006	349
9	Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits Sarvesh Bhardwaj,Sarma Vrudhula,Praveen Ghanta,Yu Cao	2006	36
10	Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage Sarvesh Bhardwaj,Yu Cao,Sarma Vrudhula	2006	14
11	Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage Sarvesh Bhardwaj,Yu Cao,Sarma Vrudhula	2006	6
12	Scaling Issues In An 0.15μm CMOS Technology With EKV3.0 DSpace - NTUA (National Technical University of Athens) ·Eleni Kitonaki,Antonios Bazigos,Matthias Bucher,Helmut Puchner,Sarvesh Bhardwaj,Y. Papananos	2006	2
13	A framework for statistical timing analysis using non-linear delay and slew models Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design ·Sarvesh Bhardwaj,Praveen Ghanta,Sarma Vrudhula	2006	45
14	Stochastic variational analysis of large power grids considering intra-die correlations Praveen Ghanta,Sarma Vrudhula,Sarvesh Bhardwaj,Rajendran Panda	2006	7
15	Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs International Conference on Computer Aided Design ·Sarvesh Bhardwaj,Sarma Vrudhula	2005	3
16	An efficient combinationality check technique for the synthesis of cyclic combinational circuits Vineet Agarwal,Navneeth Kankani,Ravishankar Rao,Sarvesh Bhardwaj,Janet Wang	2005	2
17	Leakage minimization of nano-scale circuits in the presence of systematic and random variations Sarvesh Bhardwaj,Sarma Vrudhula	2005	33
18	"AU: Timing Analysis Under Uncertainty International Conference on Computer Aided Design ·Sarvesh Bhardwaj,Sarma Vrudhula,David Blaauw	2003	41
19	/spl tau/AU: Timing analysis under uncertainty Sarvesh Bhardwaj,Sarma Vrudhula,David Blaauw	2003	38
20	Estimation of signal arrival times in the presence of delay noise Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design ·Sarvesh Bhardwaj,Sarma Vrudhula,David Blaauw	2002	7

About Sarvesh Bhardwaj

Sarvesh Bhardwaj is a scholar working on Hardware and Architecture, Statistics, Probability and Uncertainty and Software, having authored 31 papers that have together received 1.2k indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (22 papers), VLSI and FPGA Design Techniques (11 papers), Advancements in Semiconductor Devices and Circuit Design (9 papers), VLSI and Analog Circuit Testing (7 papers), Parallel Computing and Optimization Techniques (6 papers), Radiation Effects in Electronics (5 papers), Advanced Memory and Neural Computing (4 papers) and Probabilistic and Robust Engineering Design (4 papers). The work is most often cited by research in Hardware and Architecture (428 citations), Electrical and Electronic Engineering (1.1k citations) and Statistics, Probability and Uncertainty (37 citations). Sarvesh Bhardwaj has collaborated with scholars based in United States, Switzerland and Hungary. Frequent co-authors include Sarma Vrudhula, Yu Cao, Wenping Wang, Rakesh Vattikonda, Frank Liu, Shengqi Yang, Praveen Ghanta, David Blaauw, Wenping Wang and Wenping Wang. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and DSpace - NTUA (National Technical University of Athens).

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