S. Shiratake

437 total citations
21 papers, 115 citations indexed

About

S. Shiratake is a scholar working on Electrical and Electronic Engineering, Materials Chemistry and Biomedical Engineering. According to data from OpenAlex, S. Shiratake has authored 21 papers receiving a total of 115 indexed citations (citations by other indexed papers that have themselves been cited), including 21 papers in Electrical and Electronic Engineering, 5 papers in Materials Chemistry and 3 papers in Biomedical Engineering. Recurrent topics in S. Shiratake's work include Semiconductor materials and devices (12 papers), Ferroelectric and Negative Capacitance Devices (11 papers) and Advanced Memory and Neural Computing (9 papers). S. Shiratake is often cited by papers focused on Semiconductor materials and devices (12 papers), Ferroelectric and Negative Capacitance Devices (11 papers) and Advanced Memory and Neural Computing (9 papers). S. Shiratake collaborates with scholars based in Japan, South Korea and United States. S. Shiratake's co-authors include D. Takashima, I. Kunishima, K. Yamakawa, H. Shiga, A. Nitayama, T. Ozaki, Satoshi Ohtsuki, Yuji Yamada, T. Ozaki and Haruichi Kanaya and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, Solid-State Electronics and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In The Last Decade

S. Shiratake

19 papers receiving 110 citations

Peers

S. Shiratake
Sun Il Shim South Korea
Wangyong Chen China
Fabien Deprat France
Beak-Hyung Cho South Korea
S. Geißler United States
Patrick Kempf Canada
Choong-Keun Kwak South Korea
E. Vecchio Belgium
Byung-Gil Choi South Korea
O. Golonzka United States
Sun Il Shim South Korea
S. Shiratake
Citations per year, relative to S. Shiratake S. Shiratake (= 1×) peers Sun Il Shim

Countries citing papers authored by S. Shiratake

Since Specialization
Citations

This map shows the geographic impact of S. Shiratake's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by S. Shiratake with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites S. Shiratake more than expected).

Fields of papers citing papers by S. Shiratake

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by S. Shiratake. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by S. Shiratake. The network helps show where S. Shiratake may publish in the future.

Co-authorship network of co-authors of S. Shiratake

This figure shows the co-authorship network connecting the top 25 collaborators of S. Shiratake. A scholar is included among the top collaborators of S. Shiratake based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with S. Shiratake. S. Shiratake is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Karl, Eric, S. Shiratake, & Jonathan Chang. (2021). Session 24 Overview: Advanced Embedded Memories. 332–333. 1 indexed citations
2.
De, Vivek, Dennis Sylvester, James Myers, et al.. (2018). F1: Intelligent energy-efficient systems at the edge of IoT. 502–504. 1 indexed citations
3.
Takashima, D., et al.. (2015). Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs. IEEE Journal of Solid-State Circuits. 50(5). 1324–1331. 5 indexed citations
4.
Takashima, D., H. Shiga, Daisuke Hashimoto, et al.. (2011). A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs. IEEE Journal of Solid-State Circuits. 46(9). 2171–2179. 2 indexed citations
5.
Takashima, D., et al.. (2010). Highly relaible reference bitline bias designs for 64Mb and 128Mb chain FeRAMs. 1–4. 3 indexed citations
6.
Takashima, D., H. Shiga, Daisuke Hashimoto, et al.. (2010). A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM. 262–263. 13 indexed citations
7.
Takashima, D., S. Shiratake, H. Shiga, et al.. (2009). A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18(12). 1745–1752. 17 indexed citations
8.
9.
Takashima, D., S. Shiratake, H. Shiga, et al.. (2006). A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode. 459–466. 15 indexed citations
10.
Ozaki, T., Haruichi Kanaya, Y. Shimojo, et al.. (2006). A SrRuO3/IrO2 top electrode FeRAM with Cu BEOL process for embedded memory of 130nm generation and beyond. Solid-State Electronics. 50(4). 606–612. 15 indexed citations
11.
12.
Tanzawa, Tôru, Yasunori Tanaka, Tomoharu Tanaka, et al.. (2005). A Quick Boosting Charge Pump Circuit for High Density and Low Voltage Flash Memories. 65–66. 4 indexed citations
13.
Ozaki, T., Haruichi Kanaya, Y. Shimojo, et al.. (2005). A SrRuO/sub 3//IrO/sub 2/ top electrode FeRAM with cu BEOL process for embedded memory of 130nm generation and beyond. 557–560. 1 indexed citations
14.
Takashima, D., Hiroki Nakano, T. Ozaki, et al.. (2005). Folded-read And Open/folded-restore Bit-line Scheme For Giga Scale 6f2 Dram Cell. 5. 121–122.
15.
Shiratake, S., D. Takashima, Hiroki Nakano, et al.. (2005). A Staggered Nand Dram Array Architecture For A Gbit Scale Integration. 75–76.
16.
Oikawa, Keiko, et al.. (2004). Bitline/plateline reference-level-precharge scheme for high-density chainFeRAM. 36. 169–170. 1 indexed citations
17.
Shiratake, S., Yoshinori Takeuchi, Keiko Oikawa, et al.. (2003). A 32-Mb chain FeRAM with segment/stitch array architecture. IEEE Journal of Solid-State Circuits. 38(11). 1911–1919. 11 indexed citations
18.
Shiratake, S., et al.. (2003). A pseudo multi-bank DRAM with categorized access sequence. 127–130. 3 indexed citations
19.
Nakano, Hiroki, D. Takashima, K. Tsuchida, et al.. (2002). A dual layer bitline DRAM array with Vcc/Vss hybrid precharge for multi-gigabit DRAMs. 190–191. 1 indexed citations
20.
Takashima, D., M. Ohta, S. Shiratake, et al.. (1993). An experimental DRAM with a NAND-structured cell. IEEE Journal of Solid-State Circuits. 28(11). 1099–1104. 12 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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