D. Takashima

747 total citations
54 papers, 435 citations indexed

About

D. Takashima is a scholar working on Electrical and Electronic Engineering, Materials Chemistry and Computer Networks and Communications. According to data from OpenAlex, D. Takashima has authored 54 papers receiving a total of 435 indexed citations (citations by other indexed papers that have themselves been cited), including 52 papers in Electrical and Electronic Engineering, 12 papers in Materials Chemistry and 5 papers in Computer Networks and Communications. Recurrent topics in D. Takashima's work include Semiconductor materials and devices (40 papers), Ferroelectric and Negative Capacitance Devices (24 papers) and Low-power high-performance VLSI design (20 papers). D. Takashima is often cited by papers focused on Semiconductor materials and devices (40 papers), Ferroelectric and Negative Capacitance Devices (24 papers) and Low-power high-performance VLSI design (20 papers). D. Takashima collaborates with scholars based in Japan, South Korea and United States. D. Takashima's co-authors include I. Kunishima, Y. Oowaki, K. Ohuchi, Hiroki Nakano, Soichi Watanabe, T. Ozaki, A. Nitayama, S. Shiratake, F. Masuoka and K. Yamakawa and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, Solid-State Electronics and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In The Last Decade

D. Takashima

50 papers receiving 411 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
D. Takashima Japan	14	391	99	54	53	34	54	435
Farhana Parveen United States	11	232 0.6×	95 1.0×	53 1.0×	68 1.3×	37 1.1×	25	374
Kaizad Mistry United States	5	396 1.0×	133 1.3×	39 0.7×	41 0.8×	10 0.3×	8	427
N. Srivastava United States	7	454 1.2×	364 3.7×	29 0.5×	76 1.4×	19 0.6×	9	570
Sunghyun Park South Korea	8	395 1.0×	46 0.5×	65 1.2×	102 1.9×	25 0.7×	15	444
H. McAdams United States	10	415 1.1×	189 1.9×	75 1.4×	69 1.3×	22 0.6×	23	468
T. Ogawa Japan	8	182 0.5×	112 1.1×	15 0.3×	38 0.7×	15 0.4×	32	278
Campbell Millar United Kingdom	14	567 1.5×	33 0.3×	75 1.4×	53 1.0×	16 0.5×	44	600
Woojin Ahn United States	10	290 0.7×	95 1.0×	57 1.1×	33 0.6×	54 1.6×	31	387
Tsung‐Ta Wu Taiwan	13	469 1.2×	181 1.8×	18 0.3×	53 1.0×	23 0.7×	25	507
Jeff Bokor United States	6	214 0.5×	99 1.0×	18 0.3×	91 1.7×	17 0.5×	7	327

Countries citing papers authored by D. Takashima

Since Specialization

Citations

This map shows the geographic impact of D. Takashima's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by D. Takashima with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites D. Takashima more than expected).

Fields of papers citing papers by D. Takashima

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by D. Takashima. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by D. Takashima. The network helps show where D. Takashima may publish in the future.

Co-authorship network of co-authors of D. Takashima

This figure shows the co-authorship network connecting the top 25 collaborators of D. Takashima. A scholar is included among the top collaborators of D. Takashima based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with D. Takashima. D. Takashima is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Takashima, D., et al.. (2018). A 7T-SRAM With Data-Write Technique by Capacitive Coupling. IEEE Journal of Solid-State Circuits. 54(2). 596–605. 8 indexed citations

Takashima, D., et al.. (2015). Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs. IEEE Journal of Solid-State Circuits. 50(5). 1324–1331. 5 indexed citations

Takashima, D., et al.. (2010). A 100MHz ladder FeRAM design with capacitance-coupled-bitline (CCB) cell. 227–228. 6 indexed citations

Takashima, D., et al.. (2010). Highly relaible reference bitline bias designs for 64Mb and 128Mb chain FeRAMs. 1–4. 3 indexed citations

Takashima, D., S. Shiratake, H. Shiga, et al.. (2009). A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18(12). 1745–1752. 17 indexed citations

Ozaki, T., Haruichi Kanaya, Y. Shimojo, et al.. (2006). High Density and High Reliability Chain FeRAM with Damage-Robust MOCVD-PZT Capacitor with SrRuO3/IrO2 Top Electrode for 64Mb and Beyond. 8 indexed citations

Takashima, D., S. Shiratake, H. Shiga, et al.. (2006). A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode. 459–466. 15 indexed citations

Ozaki, T., Haruichi Kanaya, Y. Shimojo, et al.. (2005). A SrRuO/sub 3//IrO/sub 2/ top electrode FeRAM with cu BEOL process for embedded memory of 130nm generation and beyond. 557–560. 1 indexed citations

Watanabe, Yoshihiro, Nobuo Nakamura, D. Takashima, T. Hara, & Shunsuke Watanabe. (2003). Offset compensating bit-line sensing scheme for high density DRAMs. 116–117. 1 indexed citations

10.

Inaba, Teruhiko, D. Takashima, Y. Oowaki, et al.. (2002). A 250 mV bit-line swing scheme for a 1 V 4 Gb DRAM. 29. 99–100.

11.

Oowaki, Y., Munetaka Noguchi, Shinichi Takagi, et al.. (2002). A sub-0.1 μm circuit design with substrate-over-biasing [CMOS logic]. 88–89,. 10 indexed citations

12.

Takashima, D., et al.. (2002). A novel power-off mode for a battery-backup DRAM. 29. 109–110. 1 indexed citations

13.

Takashima, D., et al.. (2001). A 76mm 2 8Mb Chain Ferroelectric Memory.. 44. 40–41. 3 indexed citations

14.

Takashima, D.. (2001). Overview and Trend of Chain FeRAM Architecture. IEICE Transactions on Electronics. 84(6). 747–756. 5 indexed citations

15.

Takashima, D., Yoshinori Takeuchi, Y. Itoh, et al.. (2001). A 76-mm/sup 2/ 8-Mb chain ferroelectric memory. IEEE Journal of Solid-State Circuits. 36(11). 1713–1720. 25 indexed citations

16.

Takashima, D. & I. Kunishima. (1998). High-density chain ferroelectric random access memory (chain FRAM). IEEE Journal of Solid-State Circuits. 33(5). 787–792. 46 indexed citations

17.

Takashima, D., et al.. (1997). A novel power-off mode for a battery-backup DRAM. IEEE Journal of Solid-State Circuits. 32(1). 86–91. 5 indexed citations

18.

Takashima, D., M. Ohta, S. Shiratake, et al.. (1993). An experimental DRAM with a NAND-structured cell. IEEE Journal of Solid-State Circuits. 28(11). 1099–1104. 12 indexed citations

19.

Takashima, D., et al.. (1992). 10-2 Stand-by/Active Mode Logic for Sub-I V 1G/4Gb DRAMs. 2 indexed citations

20.

Tsuchida, K., Yoshihiro Watanabe, D. Takashima, et al.. (1991). A 33-ns 64-Mb DRAM. IEEE Journal of Solid-State Circuits. 26(11). 1498–1505. 15 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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