N. Kimizuka

491 total citations
18 papers, 344 citations indexed

About

N. Kimizuka is a scholar working on Electrical and Electronic Engineering, Cellular and Molecular Neuroscience and Cognitive Neuroscience. According to data from OpenAlex, N. Kimizuka has authored 18 papers receiving a total of 344 indexed citations (citations by other indexed papers that have themselves been cited), including 17 papers in Electrical and Electronic Engineering, 2 papers in Cellular and Molecular Neuroscience and 2 papers in Cognitive Neuroscience. Recurrent topics in N. Kimizuka's work include Semiconductor materials and devices (14 papers), Advancements in Semiconductor Devices and Circuit Design (13 papers) and Thin-Film Transistor Technologies (4 papers). N. Kimizuka is often cited by papers focused on Semiconductor materials and devices (14 papers), Advancements in Semiconductor Devices and Circuit Design (13 papers) and Thin-Film Transistor Technologies (4 papers). N. Kimizuka collaborates with scholars based in Japan and Taiwan. N. Kimizuka's co-authors include T. Horiuchi, Keiko Yamaguchi, Kazuo Imai, Tohru Mogami, T. Yamamoto, T. Iizuka, Robert C. Keller, K. Imai, Y. Yasuda and Yutaka Akiyama and has published in prestigious journals such as Frontiers in Neuroscience, Materials Science in Semiconductor Processing and 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

In The Last Decade

N. Kimizuka

16 papers receiving 325 citations

Peers

Countries citing papers authored by N. Kimizuka

Since Specialization

Citations

This map shows the geographic impact of N. Kimizuka's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by N. Kimizuka with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites N. Kimizuka more than expected).

Fields of papers citing papers by N. Kimizuka

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by N. Kimizuka. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by N. Kimizuka. The network helps show where N. Kimizuka may publish in the future.

Co-authorship network of co-authors of N. Kimizuka

This figure shows the co-authorship network connecting the top 25 collaborators of N. Kimizuka. A scholar is included among the top collaborators of N. Kimizuka based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with N. Kimizuka. N. Kimizuka is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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18 of 18 papers shown

#	Work	Indexed citations
1	Low-Noise Multi-Gate Pixel Transistor for Sub-Micron Pixel CMOS Image Sensors 2022 ·2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) ·Shota Kitamura, N. Kimizuka, (unknown), Koichi Baba, (unknown), (unknown), (unknown), (unknown), S. Nishimura, Akihiko Kato, (unknown), Yusuke Oike	0
2	High-Density and Large-Scale MEA System Featuring 236,880 Electrodes at 11.72μm Pitch for Neuronal Network Analysis 2020 ·(unknown), (unknown), (unknown), Koji Ogawa, (unknown), (unknown), (unknown), Aoi Odawara, (unknown), N. Kimizuka, (unknown), (unknown), Ikuro Suzuki, Yusuke Oike	11
3	A 4.8-μVrms-Noise CMOS-Microelectrode Array With Density-Scalable Active Readout Pixels via Disaggregated Differential Amplifier Implementation 2019 ·Frontiers in Neuroscience ·(unknown), (unknown), (unknown), Kenji Ikeda, (unknown), (unknown), N. Kimizuka, (unknown), (unknown), Takuya Kishimoto, Shigeki Hashimoto, Eriko Matsui, Yusuke Oike	3
4	System LSI multi-vth transistors design methodology for maximizing efficiency of body-biasing control to reduce vth variation and power consumption 2006 ·Y. Yasuda, N. Kimizuka, Yutaka Akiyama, (unknown), (unknown), Kazuo Imai	10
5	Performance improvement of CMOS device utilizing poly-Si/HfSiON gate stack and its reliability concern for 65nm technology and beyond 2006 ·Materials Science in Semiconductor Processing ·N. Kimizuka, Y. Yasuda, (unknown), (unknown), (unknown), I. Yamamoto, Kyoya Takano, Yutaka Akiyama, (unknown), Kazuo Imai	1
6	55nm CMOS Technology for Low Standby Power/Generic Applications Deploying the Combination of Gate Work Function Control by HfSiON and Stress-Induced Mobility Enhancement 2006 ·(unknown), (unknown), N. Kimizuka, Toshio Abe, I. Yamamoto, (unknown), Takashi Nakayama, Kazuya Taniguchi, (unknown), (unknown), Takuya Iwamoto, T. Tatsumi, Kazuo Imai	4
7	Ultra-low standby power (U-LSTP) 65-nm node CMOS technology utilizing HfSiON dielectric and body-biasing scheme 2005 ·N. Kimizuka, Y. Yasuda, (unknown), I. Yamamoto, Kyoya Takano, Yutaka Akiyama, Kazuo Imai	6
8	A 65nm-node LSTP(LOW Standby Power) Poly-Si/a-Si/HfSiON Transistor with High Ion-Istandby Ratio and Reliability 2004 ·Y. Yasuda, N. Kimizuka, Takeshi Iwamoto, (unknown), Takashi Ogura, (unknown), I. Yamamoto, H. Watanabe, (unknown), K. Imai	3
9	A 65nm-node LSTP (Low standby power) poly-Si/a-Si/HfSiON transistor with high I/sub on/-I/sub standby/ ratio and reliability 2004 ·Y. Yasuda, N. Kimizuka, (unknown), (unknown), Takashi Ogura, Hirohito Watanabe, (unknown), I. Yamamoto, Kimihiko Ito, (unknown), Kazuo Imai	8
10	A 0.13 μm CMOS technology integrating high-speed and low-power/high-density devices with two different well/channel structures 2003 ·Kazuo Imai, Ken Yamaguchi, N. Kimizuka, (unknown), (unknown), Atsushi Ono, (unknown), (unknown), Hiroki Fujii, (unknown), (unknown), (unknown), (unknown), Toshiyuki Horiuchi	3
11	A new degradation scheme for direct-tunneling ultrathin gate dielectric 2002 ·N. Kimizuka, Tsuyoshi Yamamoto, Tohru Mogami	1
12	Radical nitridation in multi-oxide process for 100 nm generation CMOS technology 2002 ·Y. Yasuda, N. Kimizuka, Kentaro Watanabe, (unknown), Atsushi Ono, (unknown), K. Imai, (unknown)	0
13	NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-μm gate CMOS generation 2002 ·N. Kimizuka, Keiko Yamaguchi, K. Imai, T. Iizuka, (unknown), Robert C. Keller, T. Horiuchi	109
14	A triple gate oxide CMOS technology using fluorine implant for system-on-a-chip 2002 ·(unknown), Kazuo Imai, Eiji HASEGAWA, (unknown), N. Kimizuka, Takeshi Toda, (unknown), Toshiyuki Horiuchi	5
15	Gate electrode microstructure having stacked large-grain poly-Si with ultra-thin SiO/sub x/ interlayer for reliability in sub-micrometer CMOS 2002 ·Hiroshi Itô, M. Sasaki, N. Kimizuka, (unknown), T. Ito, (unknown), (unknown), S. Watanuki, Tetsuya Ueda, Takeshi Horiuchi	2
16	CMOS device optimization for system-on-a-chip applications 2002 ·Kazuo Imai, Koji Yamaguchi, Tomoaki Kudo, N. Kimizuka, (unknown), Atsushi Ono, (unknown), (unknown), (unknown), S. Masuoka, Shotaro Ito, (unknown), Koji Ando, Eiji HASEGAWA, (unknown), (unknown), K. Yokoyama, (unknown), (unknown), T. Horiuchi	9
17	A source/drain formation technology utilizing sub-10 keV arsenic and assist-phosphorus implantation for 0.13 /spl mu/m MOSFET 1999 ·Kazuo Imai, (unknown), Koji Yamaguchi, N. Kimizuka, (unknown), Toshiyuki Horiuchi	4
18	The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling 1999 ·N. Kimizuka, T. Yamamoto, Tohru Mogami, Keiko Yamaguchi, Kazuo Imai, T. Horiuchi	165

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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