M. d'Abreu

514 total citations
33 papers, 302 citations indexed

About

M. d'Abreu is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, M. d'Abreu has authored 33 papers receiving a total of 302 indexed citations (citations by other indexed papers that have themselves been cited), including 26 papers in Electrical and Electronic Engineering, 24 papers in Hardware and Architecture and 4 papers in Computer Networks and Communications. Recurrent topics in M. d'Abreu's work include VLSI and Analog Circuit Testing (19 papers), VLSI and FPGA Design Techniques (15 papers) and Low-power high-performance VLSI design (12 papers). M. d'Abreu is often cited by papers focused on VLSI and Analog Circuit Testing (19 papers), VLSI and FPGA Design Techniques (15 papers) and Low-power high-performance VLSI design (12 papers). M. d'Abreu collaborates with scholars based in United States, Iran and United Kingdom. M. d'Abreu's co-authors include Abhijit Chatterjee, J. Khare, Ranjan Roy, Jacob A. Abraham, C. Ou-Yang, Ravi P. Gupta, Kaushik Roy, M. T. Hartman, I. Bayraktaroglu and Michael Aitken and has published in prestigious journals such as IEEE Transactions on Computers, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and Journal of Electronic Testing.

In The Last Decade

M. d'Abreu

30 papers receiving 268 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
M. d'Abreu United States 11 225 197 53 31 25 33 302
George Economakos Greece 9 141 0.6× 216 1.1× 97 1.8× 40 1.3× 16 0.6× 73 289
P. Six Belgium 8 169 0.8× 239 1.2× 75 1.4× 44 1.4× 19 0.8× 23 303
Dwight D. Hill United States 10 190 0.8× 203 1.0× 60 1.1× 25 0.8× 7 0.3× 32 284
S. Note Belgium 6 96 0.4× 241 1.2× 108 2.0× 41 1.3× 11 0.4× 13 275
Rob Aitken United States 6 356 1.6× 190 1.0× 104 2.0× 19 0.6× 42 1.7× 20 451
Yuejian Wu Canada 10 289 1.3× 263 1.3× 23 0.4× 8 0.3× 12 0.5× 28 318
P. Kozak United States 8 477 2.1× 332 1.7× 53 1.0× 32 1.0× 23 0.9× 9 519
Phu Hoang United States 4 142 0.6× 320 1.6× 138 2.6× 47 1.5× 7 0.3× 6 358
K. Masselos Greece 9 98 0.4× 181 0.9× 114 2.2× 14 0.5× 13 0.5× 42 280
Larry Cooke United States 3 90 0.4× 217 1.1× 109 2.1× 20 0.6× 9 0.4× 8 261

Countries citing papers authored by M. d'Abreu

Since Specialization
Citations

This map shows the geographic impact of M. d'Abreu's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by M. d'Abreu with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites M. d'Abreu more than expected).

Fields of papers citing papers by M. d'Abreu

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by M. d'Abreu. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by M. d'Abreu. The network helps show where M. d'Abreu may publish in the future.

Co-authorship network of co-authors of M. d'Abreu

This figure shows the co-authorship network connecting the top 25 collaborators of M. d'Abreu. A scholar is included among the top collaborators of M. d'Abreu based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with M. d'Abreu. M. d'Abreu is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
2.
Roy, Kaushik, et al.. (2009). Impact of SoC power management techniques on verification and testing. 692–695. 8 indexed citations
3.
d'Abreu, M.. (2009). From Specification to High-Volume Production. IEEE Design & Test of Computers. 26(2). 30–33.
4.
Gupta, Ravi P., et al.. (2008). Controllability of Static CMOS Circuits for Timing Characterization. Journal of Electronic Testing. 24(5). 481–496. 1 indexed citations
5.
Chatterjee, Abhijit, Ranjan Roy, & M. d'Abreu. (2005). Greedy Hardware Optimization For Linear Digital Systems Using Number Splitting And Repeated Factorization. 75. 154–159. 2 indexed citations
6.
d'Abreu, M., et al.. (2003). Flexible module generation in the FACE design environment. 396–399. 1 indexed citations
7.
d'Abreu, M., et al.. (2003). Physical assembly for analog compilation of high voltage ICs. ed 33. 14.3/1–14.3/7. 9 indexed citations
8.
d'Abreu, M., et al.. (2003). From algorithm conception to product manufacture: an automated design approach. 75. 573–576. 1 indexed citations
9.
d'Abreu, M., et al.. (2003). Scheduling and hardware sharing in pipelined data paths. 24–27. 23 indexed citations
10.
Ou-Yang, C., et al.. (2002). Wire planning for performance and yield enhancement. 113–116. 2 indexed citations
11.
Aitken, Michael, et al.. (2002). Distributed mixed level logic and fault simulation on the Pentium/sup (R/)Pro microprocessor. 160–166. 4 indexed citations
12.
Khare, J., et al.. (2002). Manufacturability analysis of standard cell libraries. 321–324. 18 indexed citations
13.
d'Abreu, M.. (2002). Manufacturing and test considerations in system-on-chip designs. 176–177. 1 indexed citations
14.
15.
Chatterjee, Abhijit, Ranjan Roy, & M. d'Abreu. (1993). Greedy hardware optimization for linear digital circuits using number splitting and refactorization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1(4). 423–431. 24 indexed citations
16.
Chatterjee, Abhijit & M. d'Abreu. (1993). The design of fault-tolerant linear digital state variable systems: theory and techniques. IEEE Transactions on Computers. 42(7). 794–808. 50 indexed citations
17.
Roy, Ranjan, Abhijit Chatterjee, J.H. Patel, Jacob A. Abraham, & M. d'Abreu. (1992). Automatic test generation for linear digital systems with bi-level search using matrix transform methods. International Conference on Computer Aided Design. 224–228. 1 indexed citations
18.
d'Abreu, M., et al.. (1989). From analog design description to layout: a new approach to analog silicon compilation. 4.4/1–4.4/4. 13 indexed citations
19.
d'Abreu, M., et al.. (1988). Analog compilation based on successive decompositions. Design Automation Conference. 369–375. 48 indexed citations
20.
d'Abreu, M.. (1985). Gate-Level Simulation. IEEE Design & Test of Computers. 2(6). 63–71. 10 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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