K. Masselos

446 total citations
42 papers, 280 citations indexed

About

K. Masselos is a scholar working on Hardware and Architecture, Computer Networks and Communications and Electrical and Electronic Engineering. According to data from OpenAlex, K. Masselos has authored 42 papers receiving a total of 280 indexed citations (citations by other indexed papers that have themselves been cited), including 35 papers in Hardware and Architecture, 20 papers in Computer Networks and Communications and 13 papers in Electrical and Electronic Engineering. Recurrent topics in K. Masselos's work include Embedded Systems Design Techniques (34 papers), Parallel Computing and Optimization Techniques (25 papers) and Interconnection Networks and Systems (16 papers). K. Masselos is often cited by papers focused on Embedded Systems Design Techniques (34 papers), Parallel Computing and Optimization Techniques (25 papers) and Interconnection Networks and Systems (16 papers). K. Masselos collaborates with scholars based in Greece, Belgium and United Kingdom. K. Masselos's co-authors include C.E. Goutis, George A. Constantinides, Qiang Liu, Francky Catthoor, Peter Y. K. Cheung, T. Stouraitis, Koen Danckaert, H. DeMan, Yiannis Andreopoulos and Nikolaos Voros and has published in prestigious journals such as IEEE Transactions on Signal Processing, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In The Last Decade

K. Masselos

37 papers receiving 261 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
K. Masselos Greece 9 181 114 98 52 42 42 280
Jani Boutellier Finland 11 161 0.9× 151 1.3× 99 1.0× 73 1.4× 41 1.0× 70 327
D. A. Geer 4 193 1.1× 171 1.5× 59 0.6× 28 0.5× 20 0.5× 5 311
Maxime Pelcat France 9 104 0.6× 83 0.7× 66 0.7× 74 1.4× 42 1.0× 48 251
Emmanuel Casseau France 9 114 0.6× 88 0.8× 66 0.7× 28 0.5× 27 0.6× 48 187
Daniel Chillet France 9 175 1.0× 114 1.0× 92 0.9× 28 0.5× 31 0.7× 42 270
A. van der Werf Netherlands 11 394 2.2× 241 2.1× 124 1.3× 54 1.0× 78 1.9× 28 458
Tim Todman United Kingdom 8 314 1.7× 187 1.6× 163 1.7× 43 0.8× 23 0.5× 39 414
P. Six Belgium 8 239 1.3× 75 0.7× 169 1.7× 15 0.3× 28 0.7× 23 303
Don Anderson 8 158 0.9× 158 1.4× 75 0.8× 19 0.4× 21 0.5× 16 294
Xiaolang Yan China 10 164 0.9× 146 1.3× 98 1.0× 24 0.5× 9 0.2× 35 268

Countries citing papers authored by K. Masselos

Since Specialization
Citations

This map shows the geographic impact of K. Masselos's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by K. Masselos with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites K. Masselos more than expected).

Fields of papers citing papers by K. Masselos

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by K. Masselos. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by K. Masselos. The network helps show where K. Masselos may publish in the future.

Co-authorship network of co-authors of K. Masselos

This figure shows the co-authorship network connecting the top 25 collaborators of K. Masselos. A scholar is included among the top collaborators of K. Masselos based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with K. Masselos. K. Masselos is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Masselos, K., et al.. (2012). Design of fixed-point rounding operators for the VHDL-2008 standard. 1–8. 2 indexed citations
2.
Liu, Qiang, George A. Constantinides, K. Masselos, & Peter Y. K. Cheung. (2009). Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems. IET Computers & Digital Techniques. 3(3). 235–246. 8 indexed citations
3.
Masselos, K. & Nikolaos Voros. (2007). Implementation of Wireless Communications Systems on FPGA-Based Platforms. EURASIP Journal on Embedded Systems. 2007. 1–9. 9 indexed citations
4.
Masselos, K., Yiannis Andreopoulos, & T. Stouraitis. (2006). Performance comparison of two-dimensional discrete wavelet transform computation schedules on a VLIW digital signal processor. IEE Proceedings - Vision Image and Signal Processing. 153(2). 173–173. 3 indexed citations
5.
Tatas, K., et al.. (2004). A reusable IP FFT core for DSP applications. III–621. 2 indexed citations
6.
Masselos, K., Francky Catthoor, C.E. Goutis, & H. DeMan. (2004). Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors. The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology. 37(1). 53–73. 1 indexed citations
7.
Masselos, K., et al.. (2003). Optimisation techniques for reducing global bus switching activity in realisations of sum-of-products computations in DSP systems. IEE Proceedings - Circuits Devices and Systems. 150(1). 16–16. 2 indexed citations
8.
Andreopoulos, Yiannis, Peter Schelkens, Gauthier Lafruit, K. Masselos, & Jan Cornelis. (2003). High-Level Cache Modeling for 2-D Discrete Wavelet Transform Implementations. The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology. 34(3). 209–226. 15 indexed citations
9.
10.
Masselos, K., et al.. (2003). Low power synthesis of sum-of-product computation in DSP algorithms. 6. 420–423. 1 indexed citations
11.
Masselos, K., et al.. (2003). Power exploration of multimedia applications realized on embedded cores. 4. 378–381. 4 indexed citations
12.
13.
Masselos, K., et al.. (2002). Memory accesses reordering for interconnect power reduction in sum-of-products computations. IEEE Transactions on Signal Processing. 50(11). 2889–2899. 4 indexed citations
14.
Masselos, K., et al.. (2002). A novel methodology for power consumption reduction in a class of DSP algorithms. 6. 199–202. 6 indexed citations
15.
Masselos, K., et al.. (2000). Low power synthesis of sum-of-products computation (poster session). 234–237. 4 indexed citations
16.
Masselos, K., et al.. (2000). A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints. The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology. 26(3). 291–317.
17.
Masselos, K., Francky Catthoor, C.E. Goutis, & Hugo De Man. (1999). Code size effects of power optimizing code transformations for embedded multimedia applications. 61–70. 1 indexed citations
18.
Masselos, K., Koen Danckaert, Francky Catthoor, C.E. Goutis, & H. DeMan. (1999). A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints. 270–272. 5 indexed citations
19.
Masselos, K., Francky Catthoor, C.E. Goutis, & H. DeMan. (1999). Interaction between sub-word parallelism exploitation and low power code transformations for VLIW multi-media processors. 52–60. 10 indexed citations
20.
Danckaert, Koen, K. Masselos, Francky Catthoor, & Hugo De Man. (1999). Strategy for power efficient combined task and data parallelism exploration illustrated on a QSDPCM video codec. Journal of Systems Architecture. 45(10). 791–808. 7 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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