Jing-Jia Liou

1.2k citations

72 papers · 945 indexed · h-index 16

Electrical and Electronic Engineering top 5%
Hardware and Architecture top 1%
Computer Vision and Pattern Recognition top 10%
Computer Networks and Communications
Software top 10%

Co-authors: Kwang‐Ting Cheng Angela Krstić A. Krstić Li-C. Wang Sandip Kundu Ying-Yen Chen Yimin Jiang Yiming Jiang
Topics: VLSI and Analog Circuit Testing (51 papers)Low-power high-performance VLSI design (33 papers)Integrated Circuits and Semiconductor Failure Analysis (30 papers)
Cited by: Hardware and Architecture Electrical and Electronic Engineering Software
Journals: BioMed Research International IEEE Transactions on Multimedia IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Partner nations: Taiwan United States Switzerland

In The Last Decade

Jing-Jia Liou

63 papers receiving 897 citations

Peers

Countries citing papers authored by Jing-Jia Liou

Since Specialization

Citations

This map shows the geographic impact of Jing-Jia Liou's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Jing-Jia Liou with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Jing-Jia Liou more than expected).

Fields of papers citing papers by Jing-Jia Liou

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Jing-Jia Liou. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Jing-Jia Liou. The network helps show where Jing-Jia Liou may publish in the future.

Co-authorship network of co-authors of Jing-Jia Liou

This figure shows the co-authorship network connecting the top 25 collaborators of Jing-Jia Liou. A scholar is included among the top collaborators of Jing-Jia Liou based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Jing-Jia Liou. Jing-Jia Liou is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Enhancing Solver Robustness through Constraint Tightening for DNN Compilation 2024 ·Chia‐Wei Chang,Jing-Jia Liou	1
2	MultiFuse: Efficient Cross Layer Fusion for DNN Accelerators with Multi-level Memory Hierarchy 2023 ·Chia‐Wei Chang,Jing-Jia Liou,Chih-Tsun Huang,Wei‐Chung Hsu,(unknown)	2
3	ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph 2021 ·(unknown),(unknown),(unknown),Jing-Jia Liou,(unknown)	2
4	A fast and accurate network-on-chip timing simulator with a flit propagation model 2015 ·(unknown),(unknown),(unknown),Jing-Jia Liou	3
5	Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications 2014 ·(unknown),Chih-Tsun Huang,(unknown),Jing-Jia Liou,(unknown),(unknown),(unknown)	2
6	Design and analysis of a many-core processor architecture for multimedia applications 2012 ·Asia-Pacific Signal and Information Processing Association Annual Summit and Conference ·(unknown),Po‐Yu Chen,(unknown),Chih-Tsun Huang,Jing-Jia Liou	2
7	Test Cost Reduction for Performance Yield Recovery by Classification of Multiple-Clock Test Data 2012 ·(unknown),(unknown),Jing-Jia Liou	0
8	On error modeling of electrical bugs for post-silicon timing validation 2012 ·Rare & Special e-Zone (The Hong Kong University of Science and Technology) ·(unknown),(unknown),Kwang‐Ting Cheng,Jing-Jia Liou	5
9	TurboVG: a HW/SW co-designed multi-core openVG accelerator for vector graphics applications with embedded power profiler 2011 ·Asia and South Pacific Design Automation Conference ·(unknown),(unknown),(unknown),Chih-Tsun Huang,Jing-Jia Liou,Yeh‐Ching Chung	0
10	Diagnosis-assisted supply voltage configuration to increase performance yield of cell-based designs 2011 ·Asia and South Pacific Design Automation Conference ·Jing-Jia Liou,Ying-Yen Chen,Chun-Chia Chen,(unknown),(unknown)	1
11	Robust Design of Biological Circuits: Evolutionary Systems Biology Approach 2011 ·BioMed Research International ·Bor‐Sen Chen,Chih‐Yuan Hsu,Jing-Jia Liou	20
12	iScan: Indirect-access scan test over HOY test platform 2009 ·(unknown),(unknown),Shi‐Yu Huang,Chih-Tsun Huang,Jing-Jia Liou,Hsi‐Pin Ma,Po-Chiun Huang,Cheng‐Wen Wu	1
13	Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques 2008 ·(unknown),(unknown),(unknown),Jing-Jia Liou,Chih-Tsun Huang,Cheng‐Wen Wu	1
14	Exploring linear structures of critical path delay faults to reduce test efforts 2006 ·Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design ·(unknown),Pei-Ying Hsieh,Jing-Jia Liou	1
15	Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step 2003 ·Design, Automation, and Test in Europe ·Angela Krstić,Li-C. Wang,Kwang‐Ting Cheng,Jing-Jia Liou,Magdy S. Abadir	34
16	Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation 2003 ·IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ·Jing-Jia Liou,Li-C. Wang,Angela Krstić,Kwang‐Ting Cheng	0
17	Diagnosis of delay defects using statistical timing models 2003 ·Rare & Special e-Zone (The Hong Kong University of Science and Technology) ·A. Krstić,Li-C. Wang,Kwang‐Ting Cheng,Jing-Jia Liou	13
18	Experience in critical path selection for deep sub-micron delay test and timing validation 2003 ·Jing-Jia Liou,Li-C. Wang,Angela Krstić,Kwang‐Ting Cheng	12
19	Path selection for delay testing of deep sub-micron devices using statistical performance sensitivity analysis 2002 ·Rare & Special e-Zone (The Hong Kong University of Science and Technology) ·Jing-Jia Liou,Kwang‐Ting Cheng,(unknown)	38
20	Enhancing test efficiency for delay fault testing using multiple-clocked schemes 2002 ·Proceedings - ACM IEEE Design Automation Conference ·Jing-Jia Liou,Li-C. Wang,Kwang‐Ting Cheng,Jennifer Dworak,M.R. Mercer,Rohit Kapur,(unknown)	20

About Jing-Jia Liou

Jing-Jia Liou is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Vision and Pattern Recognition, having authored 72 papers that have together received 945 indexed citations. Recurring topics across this work include VLSI and Analog Circuit Testing (51 papers), Low-power high-performance VLSI design (33 papers) and Integrated Circuits and Semiconductor Failure Analysis (30 papers). The work is most often cited by research in Hardware and Architecture (770 citations), Electrical and Electronic Engineering (805 citations) and Software (30 citations). Jing-Jia Liou has collaborated with scholars based in Taiwan, United States and Switzerland. Frequent co-authors include Kwang‐Ting Cheng, Angela Krstić, A. Krstić, Li-C. Wang, Sandip Kundu, Ying-Yen Chen, Yimin Jiang, Yiming Jiang, Magdy S. Abadir and Ching‐Te Chiu. Their work appears in journals such as BioMed Research International, IEEE Transactions on Multimedia and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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