Jaeseung Choi

419 total citations
23 papers, 286 citations indexed

About

Jaeseung Choi is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Industrial and Manufacturing Engineering. According to data from OpenAlex, Jaeseung Choi has authored 23 papers receiving a total of 286 indexed citations (citations by other indexed papers that have themselves been cited), including 20 papers in Electrical and Electronic Engineering, 4 papers in Biomedical Engineering and 3 papers in Industrial and Manufacturing Engineering. Recurrent topics in Jaeseung Choi's work include Advancements in Photolithography Techniques (12 papers), Semiconductor materials and devices (7 papers) and Advancements in Semiconductor Devices and Circuit Design (6 papers). Jaeseung Choi is often cited by papers focused on Advancements in Photolithography Techniques (12 papers), Semiconductor materials and devices (7 papers) and Advancements in Semiconductor Devices and Circuit Design (6 papers). Jaeseung Choi collaborates with scholars based in South Korea and United States. Jaeseung Choi's co-authors include Taejoong Song, Jong Hoon Jung, Yongho Kim, Sunghyun Park, Woojin Rim, Hyuntaek Jung, Hoonki Kim, Sanghoon Baek, Gi-Yong Yang and Changnam Park and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, Applied Sciences and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

In The Last Decade

Jaeseung Choi

18 papers receiving 253 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Jaeseung Choi South Korea 8 249 49 42 18 9 23 286
Andrew E. Carlson United States 9 349 1.4× 66 1.3× 20 0.5× 3 0.2× 6 0.7× 20 383
A.G.F. Dingwall United States 9 281 1.1× 37 0.8× 157 3.7× 3 0.2× 9 1.0× 21 292
V.V. Belyakov Russia 10 266 1.1× 34 0.7× 28 0.7× 1 0.1× 11 1.2× 61 353
Shengchang Cai United States 12 263 1.1× 33 0.7× 123 2.9× 4 0.4× 25 287
O. Semenov Canada 11 347 1.4× 78 1.6× 29 0.7× 3 0.3× 23 415
Vishal Sharma India 10 270 1.1× 57 1.2× 18 0.4× 2 0.1× 25 283
Brice Achkir United States 10 347 1.4× 23 0.5× 17 0.4× 2 0.2× 49 365
P. Karuppanan India 12 531 2.1× 12 0.2× 43 1.0× 5 0.6× 58 564
Yong-Bin Kim United States 9 325 1.3× 31 0.6× 87 2.1× 5 0.6× 30 394
Nicolas Nolhier France 10 284 1.1× 13 0.3× 45 1.1× 13 1.4× 51 315

Countries citing papers authored by Jaeseung Choi

Since Specialization
Citations

This map shows the geographic impact of Jaeseung Choi's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Jaeseung Choi with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Jaeseung Choi more than expected).

Fields of papers citing papers by Jaeseung Choi

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Jaeseung Choi. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Jaeseung Choi. The network helps show where Jaeseung Choi may publish in the future.

Co-authorship network of co-authors of Jaeseung Choi

This figure shows the co-authorship network connecting the top 25 collaborators of Jaeseung Choi. A scholar is included among the top collaborators of Jaeseung Choi based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Jaeseung Choi. Jaeseung Choi is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
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Tang, Hoyoung, et al.. (2022). 5-nm Low-Power SRAM Featuring Dual-Rail Architecture With Voltage-Tracking Assist Circuit for 5G Mobile Application. IEEE Solid-State Circuits Letters. 5. 50–53. 1 indexed citations
4.
Lu, Yi‐Chen, et al.. (2022). Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 42(7). 2331–2335. 4 indexed citations
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Song, Taejoong, Jong Hoon Jung, Woojin Rim, et al.. (2018). A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications. 198–200. 58 indexed citations
9.
Song, Taejoong, Woojin Rim, Sunghyun Park, et al.. (2016). 17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization. 306–307. 32 indexed citations
10.
Lim, Hyung-Chul, et al.. (2016). Development of Operation Software for High Repetition rate Satellite Laser Ranging. Journal of the Korean Society for Aeronautical & Space Sciences. 44(12). 1103–1111. 5 indexed citations
11.
Lim, Hyung-Chul, et al.. (2015). Design and Development of High-Repetition-Rate Satellite Laser Ranging System. Journal of Astronomy and Space Sciences. 32(3). 209–219. 8 indexed citations
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Choi, Jaeseung, et al.. (2008). Evaluation of inverse lithography technology for 55nm-node memory device. Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE. 6924. 692438–692438. 5 indexed citations
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Koo, Sunyoung, et al.. (2007). Issues and challenges of double patterning lithography in DRAM. Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE. 6520. 65200H–65200H. 25 indexed citations
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Choi, Jaeseung, et al.. (2007). DFM flow by using combination between design based metrology system and model based verification at sub-50nm memory device. Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE. 6521. 65210T–65210T.
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Choi, Jaeseung, et al.. (2006). Highly accurate modeling by using 2-dimensional calibration data set for model-based OPC verification. Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE. 6283. 62830V–62830V. 1 indexed citations
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Choi, Jaeseung, et al.. (2006). Considerations of model-based OPC verification for sub-70nm memory device. Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE. 6156. 61561D–61561D.
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Choi, Jaeseung, et al.. (2006). Positive and negative tone double patterning lithography for 50nm flash memory. Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE. 6154. 615410–615410. 41 indexed citations
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Choi, Jaeseung, et al.. (2006). New OPC verification method using die-to-database inspection. Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE. 6152. 615232–615232. 4 indexed citations
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Choi, Jaeseung, et al.. (2005). OPC accuracy enhancement through systematic OPC calibration and verification methodology for sub-100nm node. Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE. 5752. 720–720. 4 indexed citations
20.
Park, Jae‐Woo, et al.. (2003). CD control at low K1 optical lithography in DRAM device. Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE. 5038. 406–406.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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