D. Ayers

538 total citations
13 papers, 408 citations indexed

About

D. Ayers is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, D. Ayers has authored 13 papers receiving a total of 408 indexed citations (citations by other indexed papers that have themselves been cited), including 12 papers in Electrical and Electronic Engineering, 11 papers in Hardware and Architecture and 2 papers in Computer Networks and Communications. Recurrent topics in D. Ayers's work include Low-power high-performance VLSI design (11 papers), Parallel Computing and Optimization Techniques (11 papers) and Embedded Systems Design Techniques (5 papers). D. Ayers is often cited by papers focused on Low-power high-performance VLSI design (11 papers), Parallel Computing and Optimization Techniques (11 papers) and Embedded Systems Design Techniques (5 papers). D. Ayers collaborates with scholars based in United States and United Kingdom. D. Ayers's co-authors include Simon Tam, Stefan Rusu, H. Muljono, J. Chang, Ed Grochowski, Vivek Tiwari, B.S. Cherkauer, Wei Chen, Aaron D. Martin and Eddie Wang and has published in prestigious journals such as IEEE Journal of Solid-State Circuits and IEEE Design & Test of Computers.

In The Last Decade

D. Ayers

12 papers receiving 384 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
D. Ayers United States	8	314	267	147	14	14	13	408
H. Muljono United States	11	353 1.1×	278 1.0×	155 1.1×	14 1.0×	23 1.6×	21	454
Blaine Stackhouse United States	8	309 1.0×	215 0.8×	109 0.7×	10 0.7×	36 2.6×	13	372
Ana Sonia Leon United States	8	197 0.6×	200 0.7×	156 1.1×	14 1.0×	13 0.9×	12	298
Denis Dutoit France	10	197 0.6×	191 0.7×	204 1.4×	29 2.1×	6 0.4×	19	348
Jinuk Luke Shin United States	12	319 1.0×	270 1.0×	183 1.2×	23 1.6×	32 2.3×	24	450
Eric Fluhr United States	9	213 0.7×	160 0.6×	65 0.4×	8 0.6×	20 1.4×	17	273
Kyung Whan Kim South Korea	6	263 0.8×	122 0.5×	117 0.8×	10 0.7×	18 1.3×	7	328
C. Svensson Sweden	7	362 1.2×	202 0.8×	122 0.8×	10 0.7×	51 3.6×	14	418
D. Plass United States	10	276 0.9×	151 0.6×	61 0.4×	6 0.4×	10 0.7×	16	319
Daniel B. Jackson United States	6	238 0.8×	183 0.7×	94 0.6×	8 0.6×	9 0.6×	15	326

Countries citing papers authored by D. Ayers

Since Specialization

Citations

This map shows the geographic impact of D. Ayers's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by D. Ayers with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites D. Ayers more than expected).

Fields of papers citing papers by D. Ayers

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by D. Ayers. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by D. Ayers. The network helps show where D. Ayers may publish in the future.

Co-authorship network of co-authors of D. Ayers

This figure shows the co-authorship network connecting the top 25 collaborators of D. Ayers. A scholar is included among the top collaborators of D. Ayers based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with D. Ayers. D. Ayers is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

13 of 13 papers shown

1.

Rusu, Stefan, H. Muljono, D. Ayers, et al.. (2014). 5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family. 102–103. 27 indexed citations

2.

Rusu, Stefan, H. Muljono, D. Ayers, et al.. (2014). A 22 nm 15-Core Enterprise Xeon® Processor Family. IEEE Journal of Solid-State Circuits. 50(1). 35–48. 6 indexed citations

3.

Rusu, Stefan, et al.. (2010). A 45 nm 8-Core Enterprise Xeon¯ Processor. IEEE Journal of Solid-State Circuits. 45(1). 7–14. 92 indexed citations

4.

Chandrasekhar, Arun G., et al.. (2010). Chip-package-board co-design of a 45nm 8-core enterprise Xeon processor. 12. 536–542. 4 indexed citations

5.

Rusu, Stefan, et al.. (2009). Power reduction techniques for an 8-core xeon<sup>®</sup> processor. 340–343. 6 indexed citations

6.

Rusu, Stefan, et al.. (2009). A 45nm 8-core enterprise Xeon<sup>®</sup> processor. 9–12. 19 indexed citations

7.

Rusu, Stefan, et al.. (2009). A 45nm 8-core enterprise Xeon® processor. 56–57. 26 indexed citations

8.

Rusu, Stefan, Simon Tam, H. Muljono, et al.. (2007). A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache. IEEE Journal of Solid-State Circuits. 42(1). 17–25. 77 indexed citations

9.

Tam, Simon, et al.. (2006). A 65nm 95W Dual-Core Multi-Threaded Xeon� Processor with L3 Cache. 15–18. 8 indexed citations

10.

Rusu, Stefan, Simon Tam, H. Muljono, D. Ayers, & J. Chang. (2006). A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache. 315–324. 63 indexed citations

11.

Grochowski, Ed, D. Ayers, & Vivek Tiwari. (2004). Microarchitectural simulation and control of di/dt-induced power supply voltage variation. 7–16. 73 indexed citations

12.

Grochowski, Ed, D. Ayers, & Vivek Tiwari. (2003). Microarchitectural dl/dt control. IEEE Design & Test of Computers. 20(3). 40–47. 7 indexed citations

13.

Krishnamurthy, Ram, K. Soumyanath, & D. Ayers. (2002). P-boosted source followers: a robust energy-efficient bus driver technique. 35. 191–192.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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