P.E. Gronowski

1.0k citations

14 papers · 503 indexed · h-index 9

Impact in

Hardware and Architecture top 2%
- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- VLSI and Analog Circuit Testing
Electrical and Electronic Engineering top 10%
- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- VLSI and FPGA Design Techniques
- Semiconductor materials and devices

Papers in

Hardware and Architecture 13
- Parallel Computing and Optimization Techniques 9
- Embedded Systems Design Techniques 4
- VLSI and Analog Circuit Testing 2
Electrical and Electronic Engineering 13
- Low-power high-performance VLSI design 11
- VLSI and FPGA Design Techniques 5
- Semiconductor materials and devices 2

Co-authors: William J. Bowhill R.P. Preston M.K. Gowan R. Allmon B.S. Cherkauer Blaine Stackhouse Larry Biro S. Mehta
Journals: IEEE Journal of Solid-State Circuits (5 papers)2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) (1 paper)
Partner nations: United States

In The Last Decade

P.E. Gronowski

13 papers receiving 464 citations

Peers

Countries citing papers authored by P.E. Gronowski

Since Specialization

Citations

This map shows the geographic impact of P.E. Gronowski's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by P.E. Gronowski with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites P.E. Gronowski more than expected).

Fields of papers citing papers by P.E. Gronowski

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by P.E. Gronowski. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by P.E. Gronowski. The network helps show where P.E. Gronowski may publish in the future.

Co-authors

The 25 scholars most cited alongside P.E. Gronowski, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with P.E. Gronowski Line = papers co-authored together P.E. Gronowski links everyone, so they are left out of the graph.

All Works

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14 of 14 papers shown

#	Work
1	A 32nm 3.1 billion transistor 12-wide-issue Itanium^® processor for mission-critical servers سميرة أبو غزالة, Rohit Bhatia, Larry Biro, G. M. M. Lombardi, E. Fetzer, P.E. Gronowski, T. Grutkowski	2011	31
2	A 65 nm 2-Billion Transistor Quad-Core Itanium Processor IEEE Journal of Solid-State Circuits ·Blaine Stackhouse, Johana Cabinakova, Marta Caterina Bottacchi, D. K. Bradley, B.S. Cherkauer, Gaston Stiegler, Alban Gautier, Ioanna Papavassiliou- Alexiou, P.E. Gronowski, Rivas Pava, S Fraschka, 罗天琦 Luo Tianqi	2009	65
3	A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor Blaine Stackhouse, B.S. Cherkauer, Ioanna Papavassiliou- Alexiou, P.E. Gronowski, Devi Nurmala	2008	43
4	Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) ·R.P. Preston, Gianvito D’Aprile, Dan Bailey, Shane Bell, Larry Biro, William J. Bowhill, D.E. Dever, Karen F. Hood, Felipe Vieira. Santos, Н.М. ШИШХОВА, M.K. Gowan, P.E. Gronowski, LI Hai-fengb, S. Mehta, Lisa Mina, Sanskruti V. Maheshwari, B. B. Woodward, M.J. Smith	2005	28
5	A 50 MHz uniformly pipelined 64 b floating-point arithmetic processor B.J. Benschneider, William J. Bowhill, Elizabeth Cooper, Tong Ming Tang, P.E. Gronowski, Cenk Bi̇len, Waqar Ahamad Kaleem, Sanskruti V. Maheshwari, S. Samudrala	2003	0
6	A 433 MHz 64 b quad issue RISC microprocessor P.E. Gronowski, Peter Bannon, M.L. Kern, R.P. Blake-Campos, Christopher Jeppesen, William J. Bowhill, Myrna Robinson, Zhang Kai-Rui, D.R. Donchin, Richard Fromm, M.K. Gowan, Alok Jain, R O TRACCHIA, S. Mehta, J. Q. Zhang, Nataliya Rybak, Patricia Quintas, Thach Ngoc Pham, R.P. Preston, P.I. Rubinfeld	2002	6
7	A 300 MHz 64 b quad-issue CMOS RISC microprocessor William J. Bowhill, R. Allmon, Shane Bell, Elizabeth Cooper, D.R. Donchin, J.H. Edmondson, Qian Ma, P.E. Gronowski, Alok Jain, 卓雅, R O TRACCHIA, R.P. Preston, P.I. Rubinfeld, M.J. Smith, Stephen C. Thierauf, I. Bosma	2002	26
8	Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading R.P. Preston, Gianvito D’Aprile, Dan Bailey, Shane Bell, Larry Biro, William J. Bowhill, D.E. Dever, Karen F. Hood, Felipe Vieira. Santos, Н.М. ШИШХОВА, M.K. Gowan, P.E. Gronowski, LI Hai-fengb, S. Mehta, Lisa Mina, Sanskruti V. Maheshwari, B. B. Woodward, M.J. Smith	2002	28
9	High-performance microprocessor design IEEE Journal of Solid-State Circuits ·P.E. Gronowski, William J. Bowhill, R.P. Preston, M.K. Gowan, R. Allmon	1998	202
10	A 433-MHz 64-b quad-issue RISC microprocessor IEEE Journal of Solid-State Circuits ·P.E. Gronowski, William J. Bowhill, D.R. Donchin, R.P. Blake-Campos, Myrna Robinson, Lawerence E. Williams, R O TRACCHIA, S. Mehta, Nataliya Rybak, Patricia Quintas, Anne Voirin, R.P. Preston	1996	46
11	Design and Verification Strategies for Ensuring Long-Term Reliability of a 300-MHz Microprocessor 朱维莉, William J. Bowhill, P.E. Gronowski, S. Mehta, Qian Ma, E.V. Sheın, Natalia Habik-Tatarowska, Gianvito D’Aprile	1995	1
12	A pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor IEEE Journal of Solid-State Circuits ·B.J. Benschneider, William J. Bowhill, Claude Vilvens, Tong Ming Tang, P.E. Gronowski, Cenk Bi̇len, Waqar Ahamad Kaleem, Sanskruti V. Maheshwari, S. Samudrala	1989	14
13	A CMOS VAX microprocessor with on-chip cache and memory management IEEE Journal of Solid-State Circuits ·David W. Archer, Nihat Sükrü Özgören, T.F. Fox, P.E. Gronowski, Chung‐Jiuan Jeng, Philippe Moreau, Laura S. Vieira, Patricia Quintas, Reuben Allen, P.I. Rubinfeld, Yuuichirou Kiko	1987	6
14	A 32b CMOS microprocessor with on-chip instruction and data caching and memory management David W. Archer, Nihat Sükrü Özgören, Frank Fox, P.E. Gronowski, Emanuela Pasculli, Philippe Moreau, Patricia Quintas, Reuben Allen, P.I. Rubinfeld, Thomas Psota, Uldarico Inocencio Aguado Riveros, T.P. Thrush	1987	7

About P.E. Gronowski

P.E. Gronowski is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Computer Networks and Communications, Computational Theory and Mathematics and Biomedical Engineering, having authored 14 papers that have together received 503 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (11 papers), Parallel Computing and Optimization Techniques (9 papers), VLSI and FPGA Design Techniques (5 papers), Interconnection Networks and Systems (5 papers), Embedded Systems Design Techniques (4 papers), Numerical Methods and Algorithms (2 papers), Semiconductor materials and devices (2 papers) and VLSI and Analog Circuit Testing (2 papers). The work is most often cited by research in Hardware and Architecture (272 citations), Electrical and Electronic Engineering (407 citations), Computer Networks and Communications (145 citations), Computational Theory and Mathematics (26 citations) and Signal Processing (11 citations). P.E. Gronowski has collaborated with scholars based in United States. Frequent co-authors include William J. Bowhill, R.P. Preston, M.K. Gowan, R. Allmon, B.S. Cherkauer, Blaine Stackhouse, Larry Biro, S. Mehta, D.R. Donchin and M.J. Smith. Their work appears in journals such as IEEE Journal of Solid-State Circuits and 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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