Hideto Hidaka

948 total citations
54 papers, 662 citations indexed

About

Hideto Hidaka is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Hideto Hidaka has authored 54 papers receiving a total of 662 indexed citations (citations by other indexed papers that have themselves been cited), including 47 papers in Electrical and Electronic Engineering, 16 papers in Hardware and Architecture and 10 papers in Computer Networks and Communications. Recurrent topics in Hideto Hidaka's work include Semiconductor materials and devices (31 papers), Advancements in Semiconductor Devices and Circuit Design (25 papers) and Low-power high-performance VLSI design (20 papers). Hideto Hidaka is often cited by papers focused on Semiconductor materials and devices (31 papers), Advancements in Semiconductor Devices and Circuit Design (25 papers) and Low-power high-performance VLSI design (20 papers). Hideto Hidaka collaborates with scholars based in Japan, United States and Germany. Hideto Hidaka's co-authors include K. Fujishima, Takeshi Kawagoe, Yoshio Matsuda, T Yamauchi, Takashi Ito, T. Yoshihara, Kazutami Arimoto, Masakazu Aoki, K. Kimura and Hitoshi Tanaka and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Micro and IEICE Transactions on Electronics.

In The Last Decade

Hideto Hidaka

50 papers receiving 624 citations

Peers

Countries citing papers authored by Hideto Hidaka

Since Specialization

Citations

This map shows the geographic impact of Hideto Hidaka's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Hideto Hidaka with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Hideto Hidaka more than expected).

Fields of papers citing papers by Hideto Hidaka

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Hideto Hidaka. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Hideto Hidaka. The network helps show where Hideto Hidaka may publish in the future.

Co-authorship network of co-authors of Hideto Hidaka

This figure shows the co-authorship network connecting the top 25 collaborators of Hideto Hidaka. A scholar is included among the top collaborators of Hideto Hidaka based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Hideto Hidaka. Hideto Hidaka is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications 2019 ·IEICE Transactions on Electronics ·(unknown), (unknown), (unknown), (unknown), (unknown), Koji Nii, (unknown), Hiroyuki Kondo, Yoshio Matsuda, Hideto Hidaka	2
2	Embedded Flash Technology for Automotive Applications 2017 ·IEICE Technical Report; IEICE Tech. Rep. ·(unknown), (unknown), T Yamauchi, Yasuo Yamaguchi, (unknown), Hideto Hidaka	1
3	Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations 2017 ·Hideto Hidaka	14
4	A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170C 2015 ·IEEE Journal of Solid-State Circuits ·(unknown), (unknown), (unknown), (unknown), Takashi Ito, (unknown), Hideto Hidaka, T Yamauchi	23
5	40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data 2013 ·T. Kono, Takashi Ito, (unknown), (unknown), (unknown), T. Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, T Yamauchi	35
6	Evolution of embedded flash memory technology for MCU 2011 ·Hideto Hidaka	28
7	Value creation in SOC/MCU applications by embedded non-volatile memory evolutions 2007 ·(unknown), Hideto Hidaka	14
8	A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme 1999 ·IEEE Journal of Solid-State Circuits ·Hitoshi Tanaka, Masakazu Aoki, T. Sakata, (unknown), (unknown), Hideto Hidaka, (unknown), K. Kimura	41
9	Structuring a new maintenance system 1995 ·Hideto Hidaka, (unknown), (unknown)	1
10	A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs 1994 ·IEEE Journal of Solid-State Circuits ·(unknown), (unknown), (unknown), Hideto Hidaka, Kazutami Arimoto, K. Fujishima	4
11	A Smart Design Methodology with Distributed Extra Gate-Arrays for Advanced ULSI Memories (Special Issue on LSI Memories) 1993 ·IEICE Transactions on Electronics ·(unknown), Kazutami Arimoto, (unknown), Hideto Hidaka, K. Fujishima	1
12	A 34-ns 16-Mb DRAM with controllable voltage down-converter 1992 ·IEEE Journal of Solid-State Circuits ·Hideto Hidaka, Kazutami Arimoto, (unknown), (unknown), (unknown), (unknown), Toshiyuki Oishi, Shusuke Kawai, (unknown), (unknown), (unknown), (unknown), Yutaka Ohno, K. Fujishima	13
13	Cell-plate line connecting complementary bit-line (C/sup 3/) architecture for battery-operated DRAMs 1992 ·IEEE Journal of Solid-State Circuits ·(unknown), Kazutami Arimoto, Hideto Hidaka, K. Fujishima	4
14	A Dual-mode Sensing Scheme Of Capacitor Coupled EEPROM Cell For Super High Endurance 1991 ·(unknown), Hideto Hidaka, Kazutami Arimoto, K. Fujishima	0
15	A High-Density Dual-Port Memory Cell Operation For ULSI DRAMs 1991 ·Hideto Hidaka, Kazutami Arimoto, K. Fujishima	3
16	A circuit design of intelligent cache DRAM with automatic write-back capability 1991 ·IEEE Journal of Solid-State Circuits ·Kazutami Arimoto, (unknown), Hideto Hidaka, Yoshio Matsuda, (unknown)	2
17	Cell-Plate Line Connecting Complementary Bitline (c/sup 3/) Architecture For Battery Operating DRAMs 1991 ·(unknown), Kazutami Arimoto, Hideto Hidaka, K. Fujishima	3
18	A circuit design of intelligent CDRAM with automatic write back capability 1990 ·Kazutami Arimoto, (unknown), Hideto Hidaka, Yoshio Matsuda, K. Fujishima	5
19	On–chip multibit–test scheme for VLSI memories 1988 ·Electronics and Communications in Japan (Part II Electronics) ·Hideto Hidaka, K. Fujishima, (unknown), (unknown), K. Dosaka, Yasumasa Nishimura, Tsutomu Yoshihara	1
20	Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode. 1986 ·International Test Conference ·Yasumitsu Nishimura, (unknown), Hideto Hidaka, H. Ozaki, K. Fujishima, (unknown)	2

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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