Robert Wong

1.5k total citations
13 papers, 253 citations indexed

About

Robert Wong is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Condensed Matter Physics. According to data from OpenAlex, Robert Wong has authored 13 papers receiving a total of 253 indexed citations (citations by other indexed papers that have themselves been cited), including 13 papers in Electrical and Electronic Engineering, 6 papers in Hardware and Architecture and 1 paper in Condensed Matter Physics. Recurrent topics in Robert Wong's work include VLSI and Analog Circuit Testing (6 papers), Low-power high-performance VLSI design (5 papers) and Advancements in Photolithography Techniques (4 papers). Robert Wong is often cited by papers focused on VLSI and Analog Circuit Testing (6 papers), Low-power high-performance VLSI design (5 papers) and Advancements in Photolithography Techniques (4 papers). Robert Wong collaborates with scholars based in United States, Lebanon and Germany. Robert Wong's co-authors include J. Sudijono, Daquan Huang, Paolo Croce, D. Lea, R. Mann, D. Hoyniak, M. Weybright, Qun Jane Gu, C. Wann and Mau-Chung Frank Chang and has published in prestigious journals such as IBM Journal of Research and Development, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and IEEE Transactions on Semiconductor Manufacturing.

In The Last Decade

Robert Wong

13 papers receiving 239 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Robert Wong United States 5 245 42 10 7 5 13 253
Ajay N. Bhoj United States 11 306 1.2× 89 2.1× 16 1.6× 3 0.4× 16 3.2× 17 314
M. Weybright United States 4 144 0.6× 28 0.7× 8 0.8× 4 0.8× 10 147
Shien-Yang Wu Taiwan 7 165 0.7× 28 0.7× 19 1.9× 11 2.2× 12 183
J.J. Liaw Taiwan 8 250 1.0× 49 1.2× 20 2.0× 13 2.6× 14 256
Wei-Chiang Shih Taiwan 4 164 0.7× 40 1.0× 7 0.7× 4 0.8× 8 165
T. D. Haeffner United States 12 329 1.3× 123 2.9× 4 0.4× 3 0.4× 6 1.2× 23 335
Yuyun Liao United States 5 88 0.4× 70 1.7× 14 1.4× 2 0.3× 8 1.6× 10 99
Adam Makosiej France 7 115 0.5× 14 0.3× 11 1.1× 1 0.1× 7 1.4× 24 121
Enrico Monaco Italy 10 383 1.6× 24 0.6× 68 6.8× 7 1.0× 9 1.8× 23 395
Yoshihiro Shinozaki Japan 5 343 1.4× 78 1.9× 18 1.8× 9 1.8× 8 349

Countries citing papers authored by Robert Wong

Since Specialization
Citations

This map shows the geographic impact of Robert Wong's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Robert Wong with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Robert Wong more than expected).

Fields of papers citing papers by Robert Wong

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Robert Wong. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Robert Wong. The network helps show where Robert Wong may publish in the future.

Co-authorship network of co-authors of Robert Wong

This figure shows the co-authorship network connecting the top 25 collaborators of Robert Wong. A scholar is included among the top collaborators of Robert Wong based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Robert Wong. Robert Wong is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

13 of 13 papers shown
1.
Cao, Jingchen, B. L. Bhuva, Indranil Chatterjee, et al.. (2019). Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology. 1–5. 3 indexed citations
2.
Sha, Jing, et al.. (2019). Incorporating process variation contours in design rule calculation and SRAM design optimization. 8327. 33–33. 1 indexed citations
3.
Clevenger, L. A., et al.. (2016). Integrated layout based Monte-Carlo simulation for design arc optimization. Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE. 9781. 978106–978106. 1 indexed citations
4.
Ahsan, Ishtiaq, et al.. (2015). Tristate Inverter Array: A New Technology Development Yield Learning Vehicle Complementing Traditional SRAM Arrays. IEEE Transactions on Semiconductor Manufacturing. 28(4). 474–479. 2 indexed citations
5.
6.
Joshi, Rajiv, Keunwoo Kim, Rouwaida Kanj, et al.. (2014). Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23(3). 534–543. 4 indexed citations
7.
Wang, Li, et al.. (2007). Product Burn-in Stress Impacts on SRAM Array Performance. 666–667. 6 indexed citations
8.
Rosa, Giuseppe La, et al.. (2006). Impact of NBTI Induced Statistical Variation to SRAM Cell Stability. 2. 274–282. 42 indexed citations
9.
10.
Wann, C., Robert Wong, R. Mann, et al.. (2005). SRAM cell design for stability methodology. 21–22. 116 indexed citations
11.
Wong, Robert, et al.. (2004). Design and modeling of tapered LWL architecture for high density SRAM. 732–734 vol.1. 1 indexed citations
12.
Wong, Robert, et al.. (2002). DC and microwave reliability of discrete GaAs HBT devices. 1154–1157. 1 indexed citations
13.
Wong, Robert. (1990). An ac test structure for fast memory arrays. IBM Journal of Research and Development. 34(2.3). 314–324. 3 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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