D. Park

488 citations

20 papers · 278 indexed · h-index 11

Impact in

Electrical and Electronic Engineering
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Silicon Carbide Semiconductor Technologies
Computer Networks and Communications top 10%
- Advanced Data Storage Technologies

Papers in ⓘ

Electrical and Electronic Engineering 20
- Semiconductor materials and devices 17
- Advancements in Semiconductor Devices and Circuit Design 12
- Integrated Circuits and Semiconductor Failure Analysis 4
- Advanced Memory and Neural Computing 3
- Ferroelectric and Negative Capacitance Devices 3
- Low-power high-performance VLSI design 2
Computer Networks and Communications 5
- Advanced Data Storage Technologies 5

Co-authors: Jung Han Choi (1 shared paper)Kyung‐Hyun Kim (1 shared paper)Kyu Hong Kim (4 shared papers)Eunchul Yoon (4 shared papers)Ik Soo Chung (3 shared papers)B.-I. Ryu (4 shared papers)Soo‐Youn Lee (1 shared paper)Kyongmin Yeo (3 shared papers)
Journals: IEEE Electron Device Letters (3 papers)Electronics Letters (2 papers)IEEE Transactions on Electron Devices (1 paper)Applied Physics Letters (1 paper)IEEE Transactions on Device and Materials Reliability (1 paper)
Partner nations: South Korea United States Russia

In The Last Decade

D. Park

19 papers receiving 264 citations

Peers

Countries citing papers authored by D. Park

Since Specialization

Citations

This map shows the geographic impact of D. Park's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by D. Park with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites D. Park more than expected).

Fields of papers citing papers by D. Park

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by D. Park. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by D. Park. The network helps show where D. Park may publish in the future.

Co-authors

The 25 scholars most cited alongside D. Park, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with D. Park Line = papers co-authored together D. Park links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	Effects of Interface Trap Generation and Annihilation on the Data Retention Characteristics of Flash Memory Cells IEEE Transactions on Device and Materials Reliability ·J.-D. Lee, Jung Han Choi, D. Park, Kyung‐Hyun Kim	2004	103
2	Three-Dimensional MBCFET as an Ultimate Transistor IEEE Electron Device Letters ·Soo‐Youn Lee, S.-M. Kim, Eunchul Yoon, Changsuk Oh, Ik Soo Chung, D. Park, Kyu Hong Kim	2004	24
3	A Partially Insulated Field-Effect Transistor (PiFET) as a Candidate for Scaled Transistors IEEE Electron Device Letters ·Kyongmin Yeo, Changsuk Oh, S.M. Kim, M.S. Kim, Chang‐Seok Lee, Sangyoon Lee, S.Y. Han, Eunchul Yoon, H.J. Cho, D.Y. Lee, B.M. Yoon, Heung Soo Rhee, B.C. Lee, Jeong Dong Choe, Ik Soo Chung, D. Park, Kyu Hong Kim	2004	20
4	Subthreshold Degradation of Gate-all-Around Silicon Nanowire Field-Effect Transistors: Effect of Interface Trap Charge IEEE Electron Device Letters ·Bai Hong, Nam Ung Cho, Su Jung Lee, Yun Seop Yu, Lynn Choi, Yoonhyuk Jung, Keun Hwi Cho, Kyongmin Yeo, D.-W. Kim, G. Y. Jin, Kyung Shik Oh, D. Park, Sang-Hun Song, Jae-Sung Rieh, S. W. Hwang	2011	19
5	Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs) T. Park, H.J. Cho, Jeong Dong Choe, Sang-Wook Han, Seung Min Jung, J.H. Jeong, B.Y. Nam, Oh-Hyun Kwon, Jeonghoon Han, Hee Sun Kang, M. Chae, Gi-Sung Yeo, S.W. Lee, Deuk Yong Lee, D. Park, Kyu Hong Kim, Eunchul Yoon, J.H. Lee	2004	19
6	SONOS-Type FinFET Device Using P+ Poly-Si Gate and High-k Blocking Dielectric Integrated on Cell Array and GSL/SSL for Multi-Gigabit NAND Flash Memory S.‐K. Sung, D. Kim, Yun‐Song Lee, S. Kim, D. Park, B.-I. Ryu, Sanghoon Lee, Byung Chul Choi, JinHan Lee, Jeong Dong Choe, Eunyoung Cho, Y. H. Ahn, Dukhyun Choi, C.-H. Lee	2006	14
7	Trap Layer Engineered FinFET NAND Flash with Enhanced Memory Window Youngkeun Ahn, Sang‐Wook Cheong, Dongjin Lee, Sung Woo Kim, D. Park, B.-I. Ryu, Jeong Dong Choe, Jinseok Lee, Dong-Uk Choi, Eunyoung Cho, Bo-ram Choi, S.-H. Lee, S.‐K. Sung, C.-H. Lee	2006	12
8	Paired FinFET Charge Trap Flash Memory for Vertical High Density Storage S. Kim, W. Kim, Jinho Hyun, Sangjin Byun, Junemo Koo, Jaehong Lee, K. Cho, Suhwan Lim, Jung O. Park, I.-K. Yoo, C.-H. Lee, D. Park, Y. Park	2006	11
9	A 4-Bit Double SONOS Memory (DSM) with 4 Storage Nodes per Cell for Ultimate Multi-Bit Operation Changsuk Oh, Sung Woo Kim, N. Kim, Yoon-Seok Choi, K. Lee, B. Kim, Nam Ik Cho, Dong-Won Kim, D. Park, B.-I. Ryu	2006	11
10	Observation of three-dimensional shell filling in cylindrical silicon nanowire single electron transistors Applied Physics Letters ·Keun Hwi Cho, Yoonhyuk Jung, Bai Hong, S. W. Hwang, Jun‐Hyun Oh, Doyeol Ahn, S. D. Suk, Kyongmin Yeo, Dong-Won Kim, D. Park, W.-S. Lee	2007	10
11	A Unique Dual-Poly Gate Technology for 1.2-V Mobile DRAM with Simple In situ n<tex>$^+$</tex>-Doped Polysilicon IEEE Transactions on Electron Devices ·N.J. Son, Youngtek Oh, W. Kim, Seunghee Jang, Wonyoung Yang, G.H. Jin, D. Park, Kyu Hyun Kim	2004	10
12	Highly manufacturable 100 nm 6T low power SRAM with single poly-Si gate technology K. Koh, B.J. Hwang, K.H. Kwak, Y.S. Son, J.Y. Lee, Jae Hoon Jang, SungYong Seo, H.S. Kim, D. Park, K.N. Kim	2004	6
13	PMOS body-tied FinFET (Omega MOSFET) characteristics T. Park, D. Park, Jihoon Chung, Eunchul Yoon, S.M. Kim, H.J. Cho, Jeong Dong Choe, Jinsoo Choi, B.M. Yoon, Junghee Han, B.H. Kim, Sunkyu Choi, Kyu Hong Kim, J.H. Lee	2004	5
14	Technology Breakthrough of Body-Tied FinFET for sub 50 nm NOR Flash Memory Eunyoung Cho, T.-Y. Kim, Byungjin Cho, Czang-Ho Lee, Jungho Lee, Albert Fayrushin, Changhee Lee, D. Park, B.-I. Ryu	2006	5
15	Study on reliability of metal fuse for sub-100nm technology D. Park, Chang-Suk Hyun, Hyun Chul Kim, Hyuck-Jin Kang, Kang-Yoon Lee, Kyungseok Oh	2005	3
16	Reliable 2-bit/cell NVM technology using twin SONOS memory transistor Electronics Letters ·Byoong Yong Choi, B.‐G. Park, J.D. Lee, Hyung‐Joon Shin, Y.K. Lee, K. H. Bai, D.-D. Kim, Dong-Won Kim, C.-H. Lee, D. Park	2005	2
17	Ultra-low power and high speed SRAM for mobile applications using single Poly-Si gate 90 nm CMOS technology K. Koh, B.J. Hwang, G. H. Han, K.H. Kwak, Yongju Son, Jae Hoon Jang, H.S. Kim, D. Park, Kinam Kim	2003	2
18	Electrodes Based on Carbon Nanomaterials: Structure, Properties, and Application to Capacitive Deionization in Static Cells Yu. M. Volfkovich, D. A. Bograchev, A. A. Mikhalin, А. Yu. Rychagov, В. Е. Сосенкин, V. V. Milyutin, D. Park	2018	1
19	The effect of FSG stability at high temperature on stress-induced voiding in Cu dual-damascene interconnects Hyeok-Sang Oh, Jin‐Beom Chung, Jung-Woo Lee, Ki-Ho Kang, D. Park, Sang-Rok Hah, In‐Soo Cho, Kwang-Myeon Park	2004	1
20	Hybrid nanocrystal FinFET with large P/E window for MLC NAND Flash memory application Electronics Letters ·Jeong Dong Choe, Young Joon Ahn, S.-H. Lee, Dong-Hoon Jang, Young-Bae Yoon, J.J. Lee, Ik Soo Chung, K. Park, D. Park	2007	0

About D. Park

D. Park is a scholar working on Electrical and Electronic Engineering, Computer Networks and Communications, Hardware and Architecture, Automotive Engineering and Electronic, Optical and Magnetic Materials, having authored 20 papers that have together received 278 indexed citations. Recurring topics across this work include Semiconductor materials and devices (17 papers), Advancements in Semiconductor Devices and Circuit Design (12 papers), Advanced Data Storage Technologies (5 papers), Integrated Circuits and Semiconductor Failure Analysis (4 papers), Advanced Memory and Neural Computing (3 papers), Ferroelectric and Negative Capacitance Devices (3 papers), Low-power high-performance VLSI design (2 papers) and Semiconductor Quantum Structures and Devices (1 paper). The work is most often cited by research in Electrical and Electronic Engineering (257 citations), Computer Networks and Communications (66 citations), Hardware and Architecture (11 citations), Biomedical Engineering (31 citations) and Computational Theory and Mathematics (11 citations). D. Park has collaborated with scholars based in South Korea, United States and Russia. Frequent co-authors include Jung Han Choi, Kyung‐Hyun Kim, Kyu Hong Kim, Eunchul Yoon, Ik Soo Chung, B.-I. Ryu, Soo‐Youn Lee, Kyongmin Yeo, Dong-Won Kim and Keun Hwi Cho. Their work appears in journals such as IEEE Electron Device Letters, Electronics Letters, IEEE Transactions on Electron Devices, Applied Physics Letters and IEEE Transactions on Device and Materials Reliability.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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