B. Chess

1.5k total citations
22 papers, 1.0k citations indexed

About

B. Chess is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Information Systems. According to data from OpenAlex, B. Chess has authored 22 papers receiving a total of 1.0k indexed citations (citations by other indexed papers that have themselves been cited), including 12 papers in Hardware and Architecture, 12 papers in Electrical and Electronic Engineering and 7 papers in Information Systems. Recurrent topics in B. Chess's work include VLSI and Analog Circuit Testing (12 papers), Integrated Circuits and Semiconductor Failure Analysis (10 papers) and Advanced Malware Detection Techniques (6 papers). B. Chess is often cited by papers focused on VLSI and Analog Circuit Testing (12 papers), Integrated Circuits and Semiconductor Failure Analysis (10 papers) and Advanced Malware Detection Techniques (6 papers). B. Chess collaborates with scholars based in United States, Spain and Canada. B. Chess's co-authors include Gary McGraw, T. Larrabee, D.B. Lavo, F.J. Ferguson, I. Hartanto, André L. M. Freitas, J. Saxena, Kenneth M. Butler, Konstantin Beznosov and H. Balachandran and has published in prestigious journals such as IEEE Transactions on Computers, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and IEEE Software.

In The Last Decade

B. Chess

22 papers receiving 933 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
B. Chess United States 15 493 400 374 340 301 22 1.0k
Eliane Martins Brazil 15 243 0.5× 285 0.7× 405 1.1× 68 0.2× 558 1.9× 70 961
Cristina Cifuentes Australia 17 346 0.7× 443 1.1× 73 0.2× 318 0.9× 370 1.2× 67 1.0k
Christopher Salls United States 7 508 1.0× 165 0.4× 113 0.3× 914 2.7× 756 2.5× 8 1.3k
Shengjian Guo United States 12 193 0.4× 113 0.3× 80 0.2× 250 0.7× 219 0.7× 24 600
Eitan Farchi Israel 13 341 0.7× 355 0.9× 86 0.2× 102 0.3× 610 2.0× 58 1.0k
Matthias Neugschwandtner Austria 12 313 0.6× 77 0.2× 68 0.2× 632 1.9× 345 1.1× 21 807
Moonzoo Kim South Korea 20 615 1.2× 168 0.4× 56 0.1× 142 0.4× 947 3.1× 52 1.2k
Yves Deswarte France 14 578 1.2× 88 0.2× 78 0.2× 244 0.7× 91 0.3× 59 1.0k
Steve Beattie United States 9 560 1.1× 302 0.8× 182 0.5× 1.3k 3.8× 217 0.7× 10 1.9k

Countries citing papers authored by B. Chess

Since Specialization
Citations

This map shows the geographic impact of B. Chess's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by B. Chess with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites B. Chess more than expected).

Fields of papers citing papers by B. Chess

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by B. Chess. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by B. Chess. The network helps show where B. Chess may publish in the future.

Co-authorship network of co-authors of B. Chess

This figure shows the co-authorship network connecting the top 25 collaborators of B. Chess. A scholar is included among the top collaborators of B. Chess based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with B. Chess. B. Chess is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Chess, B., et al.. (2012). Guest editors' introduction: Software Assurance for the Masses. IEEE Security & Privacy. 10(3). 14–15. 3 indexed citations
2.
Chess, B., et al.. (2011). Software Security in Practice. IEEE Security & Privacy. 9(2). 89–92. 9 indexed citations
3.
McGraw, Gary & B. Chess. (2009). The Building Security in Maturity Model ({BSIMM}). 18 indexed citations
4.
Chess, B., et al.. (2008). Dynamic taint propagation: Finding vulnerabilities without attacking. Information Security Technical Report. 13(1). 33–39. 17 indexed citations
5.
Beznosov, Konstantin & B. Chess. (2008). Security for the Rest of Us: An Industry Perspective on the Secure-Software Challenge. IEEE Software. 25(1). 10–12. 10 indexed citations
6.
Chess, B., et al.. (2005). Seven Pernicious Kingdoms: A Taxonomy of Software Security Errors. IEEE Security & Privacy. 3(6). 81–84. 131 indexed citations
7.
Chess, B.. (2005). Improving computer security using extended static checking. 160–173. 57 indexed citations
8.
Chess, B. & Gary McGraw. (2004). Static analysis for security. IEEE Security & Privacy. 2(6). 76–79. 248 indexed citations
9.
Chess, B., D.B. Lavo, F.J. Ferguson, & T. Larrabee. (2002). Diagnosis of realistic bridging faults with single stuck-at information. 185–192. 27 indexed citations
10.
Lavo, D.B., B. Chess, T. Larrabee, & I. Hartanto. (2002). Probabilistic mixed-model fault diagnosis. 1084–1093. 38 indexed citations
11.
Lavo, D.B., T. Larrabee, & B. Chess. (2002). Beyond the byzantine generals: unexpected behavior and bridging fault diagnosis. 611–619. 66 indexed citations
12.
Chess, B. & T. Larrabee. (2002). Generating test patterns for bridge faults in CMOS ICs. vi. 165–170. 10 indexed citations
13.
Chess, B., André L. M. Freitas, F.J. Ferguson, & T. Larrabee. (2002). Testing CMOS logic gates for: realistic shorts. 395–402. 31 indexed citations
14.
Lavo, D.B., B. Chess, T. Larrabee, et al.. (2002). Bridging fault diagnosis in the absence of physical information. 887–893. 13 indexed citations
15.
Saxena, J., Kenneth M. Butler, H. Balachandran, et al.. (2002). On applying non-classical defect models to automated diagnosis. 748–757. 21 indexed citations
16.
Chess, B., et al.. (2002). On evaluating competing bridge fault models for CMOS ICs. 446–451. 11 indexed citations
17.
Chess, B. & T. Larrabee. (1999). Creating small fault dictionaries [logic circuit fault diagnosis]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 18(3). 346–356. 72 indexed citations
18.
Chess, B. & T. Larrabee. (1998). Logic testing of bridging faults in CMOS integrated circuits. IEEE Transactions on Computers. 47(3). 338–345. 21 indexed citations
19.
Lavo, D.B., B. Chess, T. Larrabee, & F.J. Ferguson. (1998). Diagnosing realistic bridging faults with single stuck-at information. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 17(3). 255–268. 40 indexed citations
20.
Chess, B. & T. Larrabee. (1993). Bridge fault simulation strategies for CMOS integrated circuits. 458–462. 32 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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