Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies
if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the
same subfield and year (this is the minimum needed to enter the top 1%, not the average
within it), or reaches the top citation threshold in at least one of its specific research
topics.
Voltage scheduling problem for dynamically variable voltage processors
Citations per year, relative to Tohru Ishihara Tohru Ishihara (= 1×)
peers
Larry Pileggi
Countries citing papers authored by Tohru Ishihara
Since
Specialization
Citations
This map shows the geographic impact of Tohru Ishihara's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Tohru Ishihara with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Tohru Ishihara more than expected).
This network shows the impact of papers produced by Tohru Ishihara. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Tohru Ishihara. The network helps show where Tohru Ishihara may publish in the future.
Co-authorship network of co-authors of Tohru Ishihara
This figure shows the co-authorship network connecting the top 25 collaborators of Tohru Ishihara.
A scholar is included among the top collaborators of Tohru Ishihara based on the total number of
citations received by their joint publications. Widths of edges
represent the number of papers authors have co-authored together.
Node borders
signify the number of papers an author published with Tohru Ishihara. Tohru Ishihara is excluded from
the visualization to improve readability, since they are connected to all nodes in the network.
Ishihara, Tohru, et al.. (2006). An Analysis on a Tradeoff between Reliability and Performance and a Reliable Cache Architecture for Computer Systems. 106(111). 93–98.3 indexed citations
Yasuura, Hiroto & Tohru Ishihara. (2000). System LSI design methods for low power LSIs. IEICE Transactions on Electronics. 83(2). 143–152.1 indexed citations
9.
Inoue, Koji, Tohru Ishihara, & Kazuaki Murakami. (2000). A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection. IEICE Transactions on Electronics. 83(2). 186–194.12 indexed citations
10.
Ishihara, Tohru & Hiroto Yasuura. (1999). A memory power optimization technique for application specific embedded systems. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences. 2366–2374.1 indexed citations
Ishihara, Tohru & Hiroto Yasuura. (1998). Programmable power management architecture for power reduction. IEICE Transactions on Electronics. 81(9). 1473–1479.3 indexed citations
13.
Tomiyama, Hiroyuki, Tohru Ishihara, Akihiko Inoue, & Hiroto Yasuura. (1998). Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences. 81(12). 2621–2629.3 indexed citations
14.
Ishihara, Tohru, et al.. (1998). Basic Theorems for Variable Voltage Low Power Processors. 98(66). 69–76.1 indexed citations
15.
Ishihara, Tohru, et al.. (1998). Real-Time Task Scheduling for Variable Voltage Processor. 83(113). 454–462.2 indexed citations
16.
Ishihara, Tohru & Hiroto Yasuura. (1997). Experimental Analysis of Power Estimation Models of CMOS VLSI Circuits (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems). IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences. 80(3). 480–486.2 indexed citations
17.
Ishihara, Tohru, et al.. (1997). Optimization of Supply Voltage Assignment for Power Reduction on Processor-Based Systems.3 indexed citations
Ishihara, Tohru, et al.. (1995). Some Experimental Results on Low Power Design with Gated Clock. 95(421). 7–12.1 indexed citations
20.
Fuse, G., S. Odanaka, Masaru Sasago, et al.. (1985). Trench Isolation with Boron Implanted Side-Walls for Controlling Narrow-Width Effect of n-MOS Threshold Voltages. Symposium on VLSI Technology. 58–59.1 indexed citations
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive
bibliographic database. While OpenAlex provides broad and valuable coverage of the global
research landscape, it—like all bibliographic datasets—has inherent limitations. These include
incomplete records, variations in author disambiguation, differences in journal indexing, and
delays in data updates. As a result, some metrics and network relationships displayed in
Rankless may not fully capture the entirety of a scholar's output or impact.