Tohru Ishihara
- Electrical and Electronic Engineering top 5%
- Hardware and Architecture top 0.5%
- Computer Networks and Communications top 2%
- Materials Chemistry
- Biomedical Engineering
- Co-authors
- Hiroto YasuuraKoji InoueKazuaki MurakamiHidetoshi OnoderaH. IzumiHideki YoshiokaFrederick O. AdurodijaMunekazu Motoyama
- Topics
- Low-power high-performance VLSI design (69 papers)Parallel Computing and Optimization Techniques (62 papers)Embedded Systems Design Techniques (41 papers)
- Cited by
- Hardware and ArchitectureComputer Networks and CommunicationsElectrical and Electronic Engineering
- Journals
- Applied Physics LettersJournal of Applied PhysicsIEEE Journal on Selected Areas in Communications
- Partner nations
- JapanUnited StatesIreland
In The Last Decade
Tohru Ishihara
164 papers receiving 2.0k citations
Hit Papers
Peers
Comparison fields: 5 of 88
- Electrical and Electronic Engineering 1.2k
- Hardware and Architecture 1.1k
- Computer Networks and Communications 525
- Materials Chemistry 250
- Biomedical Engineering 240
Countries citing papers authored by Tohru Ishihara
This map shows the geographic impact of Tohru Ishihara's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Tohru Ishihara with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Tohru Ishihara more than expected).
Fields of papers citing papers by Tohru Ishihara
This network shows the impact of papers produced by Tohru Ishihara. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Tohru Ishihara. The network helps show where Tohru Ishihara may publish in the future.
Co-authorship network of co-authors of Tohru Ishihara
This figure shows the co-authorship network connecting the top 25 collaborators of Tohru Ishihara. A scholar is included among the top collaborators of Tohru Ishihara based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Tohru Ishihara. Tohru Ishihara is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 2 | |
| 2 | 4 | |
| 3 | 4 | |
| 4 | Compiler Assisted Energy Reduction Techniques for Embedded Multimedia Processors | 3 |
| 5 | 6 | |
| 6 | An Analysis on a Tradeoff between Reliability and Performance and a Reliable Cache Architecture for Computer Systems | 3 |
| 7 | 13 | |
| 8 | System LSI design methods for low power LSIs | 1 |
| 9 | A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection | 12 |
| 10 | A memory power optimization technique for application specific embedded systems | 1 |
| 11 | 26 | |
| 12 | Programmable power management architecture for power reduction | 3 |
| 13 | Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches | 3 |
| 14 | Basic Theorems for Variable Voltage Low Power Processors | 1 |
| 15 | Real-Time Task Scheduling for Variable Voltage Processor | 2 |
| 16 | Experimental Analysis of Power Estimation Models of CMOS VLSI Circuits (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems) | 2 |
| 17 | Optimization of Supply Voltage Assignment for Power Reduction on Processor-Based Systems | 3 |
| 18 | 4 | |
| 19 | Some Experimental Results on Low Power Design with Gated Clock | 1 |
| 20 | Trench Isolation with Boron Implanted Side-Walls for Controlling Narrow-Width Effect of n-MOS Threshold Voltages | 1 |
About Tohru Ishihara
Tohru Ishihara is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Networks and Communications, having authored 186 papers that have together received 2.1k indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (69 papers), Parallel Computing and Optimization Techniques (62 papers) and Embedded Systems Design Techniques (41 papers). The work is most often cited by research in Hardware and Architecture (1.1k citations), Computer Networks and Communications (525 citations) and Electrical and Electronic Engineering (1.2k citations). Tohru Ishihara has collaborated with scholars based in Japan, United States and Ireland. Frequent co-authors include Hiroto Yasuura, Koji Inoue, Kazuaki Murakami, Hidetoshi Onodera, H. Izumi, Hideki Yoshioka, Frederick O. Adurodija, Munekazu Motoyama, M. Hirata and Hiroshi Tanigawa. Their work appears in journals such as Applied Physics Letters, Journal of Applied Physics and IEEE Journal on Selected Areas in Communications.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.