Kunihiro Asada
- Electrical and Electronic Engineering top 2%
- Biomedical Engineering top 5%
- Hardware and Architecture top 2%
- Computer Vision and Pattern Recognition top 5%
- Instrumentation top 5%
- Co-authors
- Makoto IkedaTetsuya IizukaToru NakuraYusuke OikeT. SuganoMasahiro SasakiMohamed AbbasShingo Mandai
- Topics
- Low-power high-performance VLSI design (84 papers)Analog and Mixed-Signal Circuit Design (71 papers)Advancements in PLL and VCO Technologies (64 papers)
- Journals
- IEEE Journal of Solid-State CircuitsIEEE Transactions on Electron DevicesJapanese Journal of Applied Physics
- Partner nations
- JapanUnited StatesSouth Korea
In The Last Decade
Kunihiro Asada
273 papers receiving 1.6k citations
Peers
Comparison fields: 5 of 65
- Electrical and Electronic Engineering 1.5k
- Biomedical Engineering 496
- Hardware and Architecture 321
- Computer Vision and Pattern Recognition 187
- Instrumentation 137
Countries citing papers authored by Kunihiro Asada
This map shows the geographic impact of Kunihiro Asada's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Kunihiro Asada with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Kunihiro Asada more than expected).
Fields of papers citing papers by Kunihiro Asada
This network shows the impact of papers produced by Kunihiro Asada. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Kunihiro Asada. The network helps show where Kunihiro Asada may publish in the future.
Co-authorship network of co-authors of Kunihiro Asada
This figure shows the co-authorship network connecting the top 25 collaborators of Kunihiro Asada. A scholar is included among the top collaborators of Kunihiro Asada based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Kunihiro Asada. Kunihiro Asada is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 13 | |
| 2 | 4 | |
| 3 | On-chip Detector for Non-Periodic High-Swing Noise Detection | 2 |
| 4 | Pixel-level color demodulation image sensor for support of image recognition | 0 |
| 5 | Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories | 2 |
| 6 | 6 | |
| 7 | A Logic-Cell-Embedded PLA (LCPLA): An Area-Efficient Dual-Rail Array Logic Architecture | 1 |
| 8 | A Row-Parallel Position Detector for High-Speed 3-D Camera Based on Light-Section Method | 5 |
| 9 | 1 | |
| 10 | 13 | |
| 11 | A smart position sensor with row parallel position detection for high speed 3-D measurement | 3 |
| 12 | High-Speed Position Detector Using Row-Parallel Architecture for Fast Collision Prevention System | 1 |
| 13 | A high–speed functional memory with a capability of hamming–distance–based data search by dynamic threshold logic circuits | 1 |
| 14 | A High-Speed PLA Using Dynamic Array Logic Circuits with Latch Sense Amplifiers | 1 |
| 15 | Approaches for Reducing Power Consumption in VLSI Bus Circuits | 2 |
| 16 | Test Structure for Characterizing Capacitance Matrix of Multi-Layer Interconnects in VLSI (Special Issue on Microelectronic Test Structures) | 1 |
| 17 | Chip fabrication for VLSI design education | 0 |
| 18 | An Image Scanning Method with Selective Activation of Tree Structure (Special Issue on New Concept Device and Novel Architecture LSIs) | 4 |
| 19 | Power Optimization for Data Compressors Based on a Window Detector in a 54x54 Bit Miltiplier | 0 |
| 20 | A Proposal of High Speed and Low Power Data Transmission Method for VLSIs by Reduced-Swing Signal (Special Section on VLSI Design and CAD Algorithms) | 1 |
About Kunihiro Asada
Kunihiro Asada is a scholar working on Hardware and Architecture, Instrumentation and Electrical and Electronic Engineering, having authored 313 papers that have together received 1.7k indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (84 papers), Analog and Mixed-Signal Circuit Design (71 papers) and Advancements in PLL and VCO Technologies (64 papers). The work is most often cited by research in Hardware and Architecture (321 citations), Instrumentation (137 citations) and Electrical and Electronic Engineering (1.5k citations). Kunihiro Asada has collaborated with scholars based in Japan, United States and South Korea. Frequent co-authors include Makoto Ikeda, Tetsuya Iizuka, Toru Nakura, Yusuke Oike, T. Sugano, Masahiro Sasaki, Mohamed Abbas, Shingo Mandai, Minoru Fujishima and Tohru Ishihara. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Electron Devices and Japanese Journal of Applied Physics.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.