Taeho Seong

647 total citations
26 papers, 484 citations indexed

About

Taeho Seong is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Astronomy and Astrophysics. According to data from OpenAlex, Taeho Seong has authored 26 papers receiving a total of 484 indexed citations (citations by other indexed papers that have themselves been cited), including 25 papers in Electrical and Electronic Engineering, 14 papers in Biomedical Engineering and 1 paper in Astronomy and Astrophysics. Recurrent topics in Taeho Seong's work include Advancements in PLL and VCO Technologies (25 papers), Radio Frequency Integrated Circuit Design (22 papers) and Analog and Mixed-Signal Circuit Design (13 papers). Taeho Seong is often cited by papers focused on Advancements in PLL and VCO Technologies (25 papers), Radio Frequency Integrated Circuit Design (22 papers) and Analog and Mixed-Signal Circuit Design (13 papers). Taeho Seong collaborates with scholars based in South Korea and United States. Taeho Seong's co-authors include Jaehyouk Choi, Yongsun Lee, Hangi Park, Seyeon Yoo, Younghyun Lim, Juyeop Kim, Heein Yoon, Mina Kim, Yongwoo Jo and Kyuho Lee and has published in prestigious journals such as Nano Energy, IEEE Journal of Solid-State Circuits and IEEE Transactions on Circuits and Systems I Regular Papers.

In The Last Decade

Taeho Seong

24 papers receiving 476 citations

Peers

Taeho Seong

EEE

CNC

Romesh Kumar Nandwana United States

Brendan Farley United States

Sang Won Son South Korea

Nereo Markulić Belgium

Mrunmay Talegaonkar United States

Min-Jae Seo South Korea

Alessio Santiccioli Italy

T. S. Arun Samuel India

R. Bouchakour France

Hangi Park South Korea

Romesh Kumar Nandwana United States

Taeho Seong

420 ×0.9

EEE

158 ×0.9

13 ×0.7

CNC

12 ×0.9

7 ×0.8

Citations per year, relative to Taeho Seong Taeho Seong (= 1×) peers Romesh Kumar Nandwana

Countries citing papers authored by Taeho Seong

Since Specialization

Citations

This map shows the geographic impact of Taeho Seong's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Taeho Seong with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Taeho Seong more than expected).

Fields of papers citing papers by Taeho Seong

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Taeho Seong. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Taeho Seong. The network helps show where Taeho Seong may publish in the future.

Co-authorship network of co-authors of Taeho Seong

This figure shows the co-authorship network connecting the top 25 collaborators of Taeho Seong. A scholar is included among the top collaborators of Taeho Seong based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Taeho Seong. Taeho Seong is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

Park, Hangi, et al.. (2022). A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. IEEE Journal of Solid-State Circuits. 57(12). 3527–3537. 18 indexed citations

Park, Hangi, et al.. (2022). A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC’s Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM. IEEE Journal of Solid-State Circuits. 57(9). 2841–2855. 34 indexed citations

Park, Hangi, et al.. (2022). A 188fs_rms-Jitter and −243d8-FoM_jitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. 2022 IEEE International Solid- State Circuits Conference (ISSCC). 378–380. 16 indexed citations

Kim, Juyeop, Yongwoo Jo, Younghyun Lim, et al.. (2021). 32.4 A 104fs_rms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique. Scholarworks@UNIST (Ulsan National Institute of Science and Technology). 448–450. 24 indexed citations

Yoo, Seyeon, et al.. (2020). A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator. IEEE Journal of Solid-State Circuits. 56(1). 298–309. 16 indexed citations

Lee, Yongsun, et al.. (2020). 17.1 A −240dB-FoM_jitter and −115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction. 266–268. 13 indexed citations

Seong, Taeho, et al.. (2020). 17.3 A −58dBc-Worst-Fractional-Spur and −234dB-FoM_jitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word. Scholarworks@UNIST (Ulsan National Institute of Science and Technology). 270–272. 36 indexed citations

Lim, Younghyun, et al.. (2019). A Fast-Transient and High-Accuracy, Adaptive-Sampling Digital LDO Using a Single-VCO-Based Edge-Racing Time Quantizer. IEEE Solid-State Circuits Letters. 2(12). 305–308. 12 indexed citations

Kim, Juyeop, et al.. (2019). A 0.1–1.5-GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC. IEEE Microwave and Wireless Components Letters. 29(8). 548–550. 5 indexed citations

10.

Kim, Juyeop, Younghyun Lim, Heein Yoon, et al.. (2019). An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators. IEEE Journal of Solid-State Circuits. 54(12). 3466–3477. 36 indexed citations

11.

Kim, Juyeop, Heein Yoon, Younghyun Lim, et al.. (2019). 16.2 A 76fs<inf>rms</inf> Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization. Scholarworks@UNIST (Ulsan National Institute of Science and Technology). 258–260. 49 indexed citations

12.

Lee, Yongsun, Taeho Seong, Seyeon Yoo, & Jaehyouk Choi. (2018). A switched-loop-filter PLL with fast phase-error correction technique. Asia and South Pacific Design Automation Conference. 307–308.

13.

Seong, Taeho, Yongsun Lee, Seyeon Yoo, & Jaehyouk Choi. (2018). A −242dB FOM and −75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC. Scholarworks@UNIST (Ulsan National Institute of Science and Technology). 396–398. 16 indexed citations

14.

Lee, Yongsun, Taeho Seong, Seyeon Yoo, & Jaehyouk Choi. (2018). A switched-loop-filter PLL with fast phase-error correction technique. Scholarworks@UNIST (Ulsan National Institute of Science and Technology). 307–308.

15.

Lee, Yongsun, Taeho Seong, Seyeon Yoo, & Jaehyouk Choi. (2017). A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique. IEEE Journal of Solid-State Circuits. 53(4). 1192–1202. 41 indexed citations

16.

Seong, Taeho, Yongsun Lee, Seyeon Yoo, & Jaehyouk Choi. (2017). A −242-dB FOM and −71-dBc reference spur ring-VCO-based ultra-low-jitter switched-loop-filter PLL using a fast phase-error correction technique. Scholarworks@UNIST (Ulsan National Institute of Science and Technology). C186–C187. 10 indexed citations

17.

Yoo, Seyeon, et al.. (2016). An Ultra-Low Power and Compact $LC$-Tank-Based Frequency Tripler Using Pulsed Input Signals. IEEE Microwave and Wireless Components Letters. 26(2). 140–142. 2 indexed citations

18.

Seong, Taeho, Jae Joon Kim, & Jaehyouk Choi. (2015). Analysis and Design of a Core-Size-Scalable Low Phase Noise <formula formulatype="inline"><tex Notation="TeX">$LC$</tex> </formula>-VCO for Multi-Standard Cellular Transceivers. IEEE Transactions on Circuits and Systems I Regular Papers. 62(3). 781–790. 4 indexed citations

19.

Lee, Yongsun, Mina Kim, Taeho Seong, & Jaehyouk Choi. (2014). A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for $\Delta\Sigma$ PLLs. IEEE Transactions on Circuits and Systems I Regular Papers. 62(3). 635–644. 18 indexed citations

20.

Seong, Taeho, Yongsun Lee, & Jaehyouk Choi. (2014). Ultralow In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration. IEEE Transactions on Circuits & Systems II Express Briefs. 61(9). 701–705. 6 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact